Energy-efficient radiation hardened SRAM cell for low voltage terrestrial applications

Prasad, Govind; Mandi, Bipin Chandra; Ali, Maifuz

doi:10.1016/j.mejo.2021.105340

Cited by 14 publications

(5 citation statements)

References 37 publications

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“…The variable parameters of the transistor, such as channel length, oxide thickness, and channel width, can alter during fabrication. A computational method called Monte Carlo (MC) Simulation, one can examine the statistical fluctuation in an output parameter of design [20]- [25]. The mean (µ) and standard deviation (σ) of these parameters are provided by MC Simulation in order to aid designers in evaluating the variation and making defensible decisions regarding design changes.…”

Section: E Statistical Analysis and Comparison Of Radiation-hardened ...mentioning

confidence: 99%

Enhanced Critical Charge (Q cr ) and Highly Reliable Read-Decoupled Radiation-Hardened 14T SRAM cell for Aerospace Application

Ahirwar,

Pattanaik,

Srivast

2023

Preprint

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Due to technological advancements, the size of transistors and the spacing between them is decreasing, resulting in a reduction in the critical charge of sensitive nodes. This decrease in critical charge makes these nodes more susceptible to disturbances and errors in static random access memory (SRAM) cells used in aerospace applications. To address this, a proposed 14T SRAM cell with polarity hardening technology is introduced in this paper, which reduces the number of sensitive nodes and enables recovery from single-event-multiple-effect (SEME) based on all single-event upset (SEU) recovery techniques. The simulation results conducted on the United Microelectronics Corporation (UMC) 65 nm CMOS commercial standard process demonstrate that the proposed 14T SRAM cell reduces both SEU and SEME. A comparative study is performed between the proposed 14T cell and other radiation-hardened SRAM cells, including DICE, SAR14T, RSP14T, RHBD14T, and NRHC14T, to assess the relative performance of the proposed cell. The proposed 14T cell for SRAM exhibits 40.42% and 21.39% improvements in write stability compared to existing cells like DICE and RSP14T, as well as 25.08% and 19.09% improvements in read stability compared to RHBD14T and RSP14T. It also shows enhancements of 81.88%, 76.82%, 57.83%, and 10.25% in critical charge value compared to RHBD14T, NRHC14T, SAR14T, and RSP14T, respectively, better stability, and improved overall performance, making it suitable for aerospace applications. Monte Carlo (MC) simulations have verified its ability to recover from SEU and SEME, with zero percent failure probability during read, write, and hold operations at different supply voltages.

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Section: E Statistical Analysis and Comparison Of Radiation-hardened ...mentioning

confidence: 99%

Enhanced Critical Charge (Q cr ) and Highly Reliable Read-Decoupled Radiation-Hardened 14T SRAM cell for Aerospace Application

Ahirwar,

Pattanaik,

Srivast

2023

Preprint

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“…As illustrated in Fig. 5(a) [28], the BLB value discharged via the N1, N3, N7, P5 and N5 transistors. This process will continue until the N2 and N4 transistors switched ON.…”

Section: ) Read Analysismentioning

confidence: 99%

“…5(b) by considering the ref. [28]. The primary storage node's voltage difference is increased by the cross-coupled N3 and N4 transistors [24], [29].…”

Section: ) Write Analysismentioning

confidence: 99%

Double Node Upset Immune RHBD-14T SRAM Cell for Space and Satellite Applications

Mukku,

Lorenzo

2023

IEEE Access

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Deep sub-micron memory devices play a crucial role in space electronic applications due to their susceptibility to single-event upset and double-node upset types of soft errors. When a charged particle from space hit a scaled memory circuit, the critical charge of sensitive storage nodes drops, and a node upset happens across the storage nodes. This paper describes the soft error immune RHBD-14T SRAM cell (SEI-14T) for space and satellite applications. The SEI-14T memory cell consists of two latch circuits coupled in a self-recovering, state-restoring feedback manner. In addition, SEI-14T memory cell mitigate single event upset (SEU) in all sensitive nodes and a portion of double node upset. By considering the sensitive node area separation approach, the remaining upset pairs were recovered. To show the relative performance of the SEI-14T, the state-of-the-art of other radiation-resistant memory cells, such as the Quatro-10T, RHM-12T, RHD-12T, RSP-14T, RHPD-12T, RH-14T, EDP-12T, and QCCS-12T are considered. Compared to all other mentioned memory cells, SEI-14T has superior write stability, and greater read stability than all other memory cells. Furthermore, at 0.8 V supply voltage, SEI-14T minimizes 23%, 12.28% and 20.82% of read access time, write access time and static power consumption respectively compared to existing memory cells. Moreover, the critical charge of SEI-14T was 6.56x/ 3.4x/ 5.75x/ 2.54x/ 2.47x/ 1.81x/ 1.63x/ 1.44x times larger than Quatro-10T/ RHM-12T/ RHD-12T/ RSP-14T/ RHPD-12T/ RH-14T/ EDP-12T/ QCCS-12T memory cells.INDEX TERMS Critical charge, double node upset (DNU), ion track, PVT analysis, radiation hardening, sensitive node, single event upset, soft errors.

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“…Its principle is to combine circuit structure and layout structure and use circuit feedback loop to realize data recovery of storage nodes. The design methods are mainly divided into the following types: (1) radiation‐hardened design based on cross‐coupling feedback structure, such as We‐Quatro, 12 QUCCE12T, 13 SIS10T, 14 and 12T 15 circuits, which use multi‐channel read/write and feedback loop multiplexing to improve the circuit performance, but the multi‐node upset recovery performance is limited; (2) using the characteristics of transistor charge collection, such as polarity hardening method, node data can only upset to one direction, such as RHPD‐12T, 16 SARP12T, 17 and SEA14T 18 ; this method reduces the node voltage swing, often resulting in the reduction of cell noise tolerance; (3) combine circuit design with layout hardened design methods, such as RSP14T, 19 which requires a large amount of computing resources due to its complicated verification method.…”

Section: Introductionmentioning

confidence: 99%

Write‐enhanced and radiation‐hardened SRAM for multi‐node upset tolerance in space‐radiation environments

Zhao

Dong

Peng

et al. 2022

Circuit Theory & Apps

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Summary As transistor feature size is scaling down, the probability of charge sharing in a space‐radiation environment increases because of the reduced distance between adjacent transistors. The single‐event multiple‐node upset (SEMNU) caused by charge sharing is a major source of data errors in high‐density static random‐access memory (SRAM). In this paper, a radiation‐hardened SRAM using polarity hardening is proposed. Compared to other cells (RHPD‐12T, RSP14T, SEA14T, We‐Quatro, QUCCE12T, SARP12T, SIS10T, and 12T), the proposed RHC‐14T cell saves 8.47%, 91.34%, 162.71%, ‐20.63%, −20.50%, 113.18%, 63.27%, and 20.60% of the read‐delay time and 7.96%, 66.17%, 68.16%, 57.71%, 22.39%, 12.44%, 1,010.45%, and 13.43% of the write‐delay time, respectively. Moreover, this excellent performance entails only minimal power consumption. The proposed cell can work well in the radiation‐intensive space environment.

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Energy-efficient radiation hardened SRAM cell for low voltage terrestrial applications

Cited by 14 publications

References 37 publications

Enhanced Critical Charge (Q cr ) and Highly Reliable Read-Decoupled Radiation-Hardened 14T SRAM cell for Aerospace Application

Enhanced Critical Charge (Q cr ) and Highly Reliable Read-Decoupled Radiation-Hardened 14T SRAM cell for Aerospace Application

Double Node Upset Immune RHBD-14T SRAM Cell for Space and Satellite Applications

Write‐enhanced and radiation‐hardened SRAM for multi‐node upset tolerance in space‐radiation environments

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