Energy Management Techniques for SOC Design

Abstract

One of the biggest problems in complicated and high-performance SoC design is management of energy and/or power consumption. In this chapter, we present energy management techniques in system design including HW and SW, SoC architecture and logic design. Dynamic power consumption is the major factor of energy consumption in the current CMOS digital circuits. The dynamic power consumption is affected by supply voltage, load capacitance and switching activity. We present approaches to controlling supply voltage, load capacitance and switching activity dynamically and statically in system architecture and algorithm design levels. We also discuss on the memory architecture for reducing power and energy in HW and SW co-design of SoC. In the future CMOS technology, leakage power consumption becomes dominant, because the threshold voltages are scaled as the transistor size shrinks. We summarize the techniques for reducing leakage power in system architecture design. The contents of the chapter include the following issues;(1) power and energy consumptions in SoC design, (2) tradeoff between energy and performance, (3) tradeoff among energy, QoS (i.e., latency and computational precision), reliability, and flexibility (4) techniques for reducing dynamic power consumption, and (5) leakage power reduction techniques.

Power-Gated Arithmetic Circuits for Energy-Precision Tradeoffs in Mobile Graphics Processing Units

“…Varying the quality of results in favor of faster or more reliable operation has also been examined, from Lafruit et al's [14] work on graceful degradation of 3D algorithms, to Yasuura et al's [15] treatment of energy-performance tradeoffs in computational systems, to Yeh et al's [16] [17] exploration of error tolerance in physics-based animation. None of these approaches, however, has systematically explored energy-precision tradeoffs in a graphics pipeline.…”

Multi-functional systolic array with reconfigurable micro-power processing elements

“…Problems related to power-consumption in SoC designs were considered in [7]. In [8] a clock gating technique was employed to minimize power-consumption of multi-functional processing element (PE).…”