Energy minimization in dynamic supply voltage scaling systems using data dependent voltage level selection

Chandrasena, Lama H.; Liebelt, M.J.

doi:10.1109/iscas.2000.856381

Cited by 6 publications

(5 citation statements)

References 9 publications

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“…However, the drawback of using a lower VDD is the performance degradation. Adaptive-VDD and Multiple-VDD techniques can reduce the power consumption without performance degradation [2][3][4][5][6][7]. DSP (Digital Signal Processing) chips and ALUs (Arithmetic Logic Unit) are most commonly used components of mobile products requiring low power dissipation.…”

Section: P = α⋅F⋅c⋅vddmentioning

confidence: 99%

“…In the specific design shown in Fig. 4, C [5] is forwarded to C [9] if SW0 is activated, that is, if propagate signals, P [9:6], are all "1".…”

Section: Carry-skip Scheme Compensating Delay Overheadmentioning

confidence: 99%

“…For example, when A[9:6]="1111" and B[9:6]="0000", P[9:6]="1111", the carry-in C [5] propagates to the carry-out C [9] directly. On the other hand, if A[9:6]="1111" and B[9:6]="0100", the carry-out C [8] is generated by A [8] and B [8] and propagates to C [9] regardless of the state of C [5]. Hence, when P[9:6]="1111", we can skip 4-bit RCA having inputs A[9:6] and B [9:6], thereby, we can reduce the worst propagation delay.…”

Section: Carry-skip Scheme Compensating Delay Overheadmentioning

confidence: 99%

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Low-power carry-select adder using adaptive supply voltage based on input vector patterns

Suzuki

Jeong

Roy

2004

Proceedings of the 2004 International Symposium on Low Power Electronics and Design

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Demands for the low power VLSI have been pushing the aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose Adaptive Supply Voltage Carry-Select Adder (CSA) based on the input vector patterns. A proposed level converter based on the Complementary Pass Transistor Logic (CPL) cancels out the delay penalty of level conversion. We achieved 26% power improvement on a 128-bit CSA prototype over a conventional design with same performance.

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Section: P = α⋅F⋅c⋅vddmentioning

confidence: 99%

“…In the specific design shown in Fig. 4, C [5] is forwarded to C [9] if SW0 is activated, that is, if propagate signals, P [9:6], are all "1".…”

Section: Carry-skip Scheme Compensating Delay Overheadmentioning

confidence: 99%

Section: Carry-skip Scheme Compensating Delay Overheadmentioning

confidence: 99%

See 1 more Smart Citation

Low-power carry-select adder using adaptive supply voltage based on input vector patterns

Suzuki

Jeong

Roy

2004

Proceedings of the 2004 International Symposium on Low Power Electronics and Design

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“…Techniques such as doping profile modification and adaptive body-biasing have been proposed as means to mitigate such timing fluctuations. Similar to other power reduction techniques such as dynamic voltage scaling, forced transistor stacking, and power gating [3][4][5], maintaining the integrity of the digital signal is critical to achieve reliability under ultra-low voltages.…”

Section: Introductionmentioning

confidence: 99%

A Comparative Study of Ultra-Low Voltage Digital Circuit Design

Arthurs¹,

Roark²,

Di³

2012

VLSICS

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Ultra-low voltage digital circuit design is an active research area, especially for portable applications such as wearable electronics, intelligent remote sensors, implantable medical devices, and energy-harvesting systems. Due to their application scenarios and circuit components, two major goals for these systems are minimizing energy consumption and improving compatibility with low-voltage power supplies and analog components. The most effective solution to achieve these goals is to reduce the supply voltage, which, however, raises the issue of operability. At ultra-low supply voltages, the integrity of digital signals degrades dramatically due to the indifference between active and leakage currents. In addition, the system timing becomes more unpredictable as the impact of process and supply voltage variations being more significant at lower voltages. This paper presents a comparative study among three techniques for designing digital circuits operating at ultra-low voltages, i.e., Schmitt-triggered gate structure, delayinsensitive asynchronous logic, and Fully-Depleted Silicon-on-Insulator technology. Results show that despite the tradeoffs, all eight combinations of these techniques are viable for designing ultra-low voltage circuits. For a given application, the optimum circuit design can be selected from these combinations based on the lowest voltage, the dynamic range, the power budget, the performance requirement, and the available semiconductor process node.

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“…For processors, the basic techniques involve dynamic voltage and frequency scaling (DVFS) [Burd et al 2000;Chandrasena and Liebelt 2000;Lu et al 2002;Simunic et al 2001;Yan et al 2003;Choi et al 2004;Ishihara and Yasuura 1998;Cho et al 2006] and for subsystems such as disk drives and other peripherals, the methods involve various forms of speed control, and are generally referred to as dynamic power management [Benini and De Micheli 19:4 • K. Lee et al to electrical energy without combustion. A DMFC can be classified as a PEMFC, but in general a distinction is made between the two.…”

Section: Introductionmentioning

confidence: 99%

A fuel-cell-battery hybrid for portable embedded systems

Lee

Chang

Zhuo

et al. 2008

ACM Trans. Des. Autom. Electron. Syst.

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This article presents our work on the development of a fuel cell (FC) and battery hybrid (FC-Bh) system for use in portable microelectronic systems. We describe the design and control of the hybrid system, as well as a dynamic power management (DPM)-based energy management policy that extends its operational lifetime. The FC is of the proton exchange membrane (PEM) type, operates at room temperature, and has an energy density which is 4-6 times that of a Li-ion battery. The FC cannot respond to sudden changes in the load, and so a system powered solely by the FC is not economical. An FC-Bh power source, on the other hand, can provide the high energy density of the FC and the high power density of a battery.In this work we first describe the prototype FC-Bh system that we have built. Such a prototype helps to characterize the performance of a hybrid power source, and also helps explore new energy management strategies for embedded systems powered by hybrid sources. Next we describe a Matlab/Simulink-based FC-Bh system simulator which serves as an alternate experimental platform and that enables quick evaluation of system-level control policies. Finally, we present an optimization framework that explicitly considers the characteristics of the FC-Bh system and is aimed at minimizing the fuel consumption. This optimization framework is applied on top of a prediction-based DPM policy and is used to derive a new fuel-efficient DPM scheme. The proposed scheme demonstrates up to 32% system lifetime extension compared to a competing scheme when run on a real trace-based MPEG encoding example.

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Energy minimization in dynamic supply voltage scaling systems using data dependent voltage level selection

Cited by 6 publications

References 9 publications

Low-power carry-select adder using adaptive supply voltage based on input vector patterns

Low-power carry-select adder using adaptive supply voltage based on input vector patterns

A Comparative Study of Ultra-Low Voltage Digital Circuit Design

A fuel-cell-battery hybrid for portable embedded systems

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