Energy-performance design space exploration in SMT architectures exploiting selective load value predictions

Gellert,; Palermo,; Zaccaria,; Florea,; Vintan,; Silvano,

doi:10.1109/date.2010.5457197

Cited by 7 publications

(8 citation statements)

References 14 publications

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“…(All pipeline stages width=1). As can be seen in Fig.1 results show that although having bigger cache is one of the performance improvement approaches in embedded processors [5,[12][13][14] however by increasing the cache size over a threshold level, performance improvement is saturated and then, decreased. It's because , increasing the cache size, leads to more cache access delays and means that increasing the cache size always is not applicable as an approach to have better performance for embedded processors.…”

Section: A Performance Analysismentioning

confidence: 77%

Cache power and performance tradeoffs for embedded applications

Alipour

Salehi

Moshari

2011

2011 IEEE International Conference on Computer Applications and Industrial Electronics (ICCAIE)

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As embedded applications have became more complex, design of embedded processors has created a research area for low power and yet high performance architectures. Power consumption is as important as performance in battery-powered embedded systems and in future, embedded processors are to process more computationintensive applications with limited power budgets. Therefore, power consumption of theses processors will become more critical. According to the high contribution of memory access power in total power consumption of embedded systems, memory architecture of embedded systems strongly influences the system design objectives. Cache memories are usually used to improve the performance and power consumption by bridging the gap between the speed and power consumption of the main memory and CPU, therefore, the system performance and power consumption is severely related to the average memory access time and power consumption which makes the cache architecture as a major concern in designing embedded processors. Therefore, the embedded system designer requires a comprehensive design space exploration for memory architecture. In this paper we explore the design space of cache in embedded processors to find out the cache sizes which have the optimum performance/power consumption in embedded applications.

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Section: A Performance Analysismentioning

confidence: 77%

Cache power and performance tradeoffs for embedded applications

Alipour

Salehi

Moshari

2011

2011 IEEE International Conference on Computer Applications and Industrial Electronics (ICCAIE)

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“…The target architecture is a superscalar Alpha AXP 21264 processor augmented with a direct mapped SLVP of 1024 entries, access latency of one cycle and prediction latency of three cycles [3]. It has a register file of [32 int/32 fp] * 8, a reorder buffer (ROB) of 128 entries and a load/store queue (LSQ) of 48 entries.…”

Section: Simulation Methodologymentioning

confidence: 99%

“…The SLVP was already used in our previous papers [1,3] and other load value predictors have been proposed in [7,8]. Different architectural support techniques for value prediction or energy efficient approaches that speculate on the results of load instructions in order to speed-up the execution are presented in [9,10].…”

Section: Related Workmentioning

confidence: 99%

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Multi-objective optimisations for a superscalar architecture with selective value prediction

Gellért¹,

Calborean²,

Vintan³

et al. 2012

IET Comput. Digit. Tech.

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This work extends an earlier manual design space exploration (DSE) of the authors' developed selective load value prediction-based superscalar architecture to the L2 unified cache. After that the authors perform an automatic DSE using a special developed software tool by varying several architectural parameters. The goal is to find optimal configurations in terms of cycles per instruction and energy consumption. By varying 19 architectural parameters, as the authors proposed, the design space is over 2.5 millions of billions configurations which obviously means that only a heuristic search can be considered. Therefore the authors propose different methods of automatic DSE based on their developed framework for automatic design space exploration which allow them to evaluate only 2500 configurations of the above mentioned huge design space! The experimental results show that their automatic DSE provides significantly better configurations than the previous manual DSE approach, considering the proposed multi-objective approach.

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“…On the other hand, although cache is primarily used to overcome the performance gap between processor and main memory [5,6], however, researches show that in processors, the major part of energy is consumed in caches [6][7][8][9][10][11][12][13][14]. Hence, the methods which lead to optimum performance/power ratio for embedded processors will be applicable.…”

Section: Introductionmentioning

confidence: 99%

Multi objective design space exploration of cache for embedded applications

Alipour¹,

Taghdisi

Sadeghzadeh

2012

2012 25th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)

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High contribution of cache access power in the total power consumption of embedded processors has made it a major concern in embedded system designs. By technology scaling, leakage power has created more stress on design constraint and power budget of embedded processors. Therefore; designers require a comprehensive design space exploration of cache architecture. In this paper we find out the optimum performance per power consumption points for cache sizes based on design space exploration using a new energy model considering dynamic and leakage energy of cache for embedded applications. Full exploration is performed based on different feature sizes to find out the effect of technology scale down on power parameters of cache. Results show that in different feature sizes 30% of static power and 43 % of total power of an embedded core is consumed in the cache hierarchy in average. It means based on this work in smaller feature sizes and for embedded application that can tolerate performance lose up to 3%, we should select smaller cache hierarchy to deliver better performance per power as the most important parameter in designing embedded systems.

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Energy-performance design space exploration in SMT architectures exploiting selective load value predictions

Cited by 7 publications

References 14 publications

Cache power and performance tradeoffs for embedded applications

Cache power and performance tradeoffs for embedded applications

Multi-objective optimisations for a superscalar architecture with selective value prediction

Multi objective design space exploration of cache for embedded applications

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