Engineered Si wafers: On the role of oxide heterostructures as buffers for the integration of alternative semiconductors

Abstract

Engineered Si wafer systems present an important materials science approach to further improve the performance of Si‐based micro‐ and nanoelectronics. This is due to the potential to integrate alternative semiconductor layers on the mature Si wafer technology platform which are otherwise too expensive or even impossible to grow in bulk form in the required quality and quantity. Ge is attracting increasing research interest because it is for example a promising material for high mobility channel CMOS technologies as well as a mediator material to achieve the manufacturing of III‐V/Si hybrid devices. The integration of Ge on Si wafers is today either achieved by a combination of layer transfer and wafer bonding techniques or by a sequence of subsequent, epitaxial thin film deposition growth steps. In the latter case, the traditional approach to integrate Ge layers of low defect densities is given by the use of compositionally graded SiGe heterostructures. As this approach suffers however from required SiGe buffer thicknesses on the micrometer scale, making integrated circuit processing difficult, research on the development of innovative buffer heteroepitaxy approaches is intensively pursued. A new interesting class of buffer materials with a high degree of flexibility is given by oxide heterostructures. Using the integration of single crystalline Si and Ge on the Si(111) material platform via oxide heterostructures as an example, the flexibility of engineered oxide heterostructures to control important epitaxy parameters is demonstrated. In this study, epitaxial Si(111) and Ge(111) layers were grown on cubic Y2O3(111)/cubic Pr2O3(111)/Si(111) and Pr2O3(111)/Si(111) support systems, respectively. The structural properties of the Si‐on‐Insulator (SOI) and Ge‐on‐Insulator (GOI) heterostructures were characterized in detail by a combination of laboratory‐ and synchrotron‐based methods. As main result, both the epitaxial Si(111) and Ge(111) films were shown to be atomically smooth and single crystalline (i.e. free of stacking twins). Defect engineering approaches need to be applied in future to reduce stacking faults (e.g. microtwins) which are identified as the major defect mechanism in the epitaxial Si(111) and Ge(111) films. (© 2009 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

GaP collector development for SiGe heterojunction bipolar transistor performance increase: A heterostructure growth study

“…5(b)). 39,40 To study the microtwin formation in GaP layer in more detail, a circular /-scan (0 À360 ) at fixed position v ¼ 16 and on the 2h value of GaP(111) was performed. Figure 5 Taking the use of a 4 off-orientated Si(001) substrate into account (Fig.…”

Dielectric properties of single crystalline PrO2(111)/Si(111) heterostructures: Amorphous interface and electrical instabilities

“…Recently, single crystalline oxide heterostructures were proposed as a buffer approach to tailor important heteroepitaxy parameters ͑lattice mismatch adjustment, surface wetting behavior, impurity diffusion, etc.͒ for achieving the growth of high quality semiconductor/insulator/Si heterostructures. 7 For example, recent works concentrated on the integration of the following single crystalline semiconductor materials on Si via oxide heterostructures: indium phosphide ͑InP͒ on Gd 2 O 3 / Si ͑Ref. 8͒ and SrTiO 3 / Si; 9 GaN on Al 2 O 3 ; 10-12 Si on Y 2 O 3 / Si, [13][14][15][16] on La x Y z O 3 / Si, 17,18 as well as on CeO 2 / Si; 19,20 and Ge on BaTiO 3 / SrTiO 3 / Si ͑Ref.…”

Single crystalline Sc2O3/Y2O3 heterostructures as novel engineered buffer approach for GaN integration on Si (111)

“…14,15 Indeed, the use of oxide buffers could also be beneficial for GaN integration on Si ͑Ref. 14,15 Indeed, the use of oxide buffers could also be beneficial for GaN integration on Si ͑Ref.…”