Engineering of tunnel barrier for highly integrated nonvolatile memory applications

Fabrication of Sn@Al2O3 Core-shell Nanoparticles for Stable Nonvolatile Memory Applications

“…Secondly, metallic NCs can be employed as discrete charge sites [3,4,5], which reduce the spurious effects caused by traps at the NCs/oxide interface, and enhance the charge storage capacity due to multiple electron trapping at the NCs [3]. Thirdly, a low- k /high- k dielectric stacked tunneling oxide barrier can be employed instead of a single dielectric layer of SiO 2 [6,7,8], with one example including SiO 2 /Al 2 O 3 , which produces a device exhibiting a high charge storage stability. These three factors can be achieved in a facile manner by forming metal@high- k dielectric core-shell nanoparticles (NPs) between tunneling and control oxide layers.…”

Optimization of high-k composite dielectric materials of variable oxide thickness tunnel barrier for nonvolatile memory

“…Memory capacity and performance must scale as the flash memory size has been scaled to maintain the device performance such as P/E voltage, P/E time, better retention and endurance. Nevertheless, the scaling becomes challenging because of the high electric fields acquired in the programming/erasing process [1] and direct tunneling effect [2].…”

“…As one of the effective solutions, the inception of the different dielectric with high dielectric constant (high-k) materials stacks to engineer the tunnel oxide is proposed. Many researches have been reported about the tunnel barrier engineering (TBE) approach to analyze the performance before and after the inception of high-k dielectric materials [1][2][3][4]. TBE technology is an approach to modify the tunnel barrier by incorporating the high-k dielectric materials in which the high-k dielectric will extend scalability of the same equivalent oxide thickness (EOT) by applying a thicker physical tunnel stack.…”

Multi-Layered Al2O3/HfO2/SiO2/Si3N4/SiO2Thin Dielectrics for Charge Trap Memory Applications

“…3 An extensive research has been performed on TANOS cell in the last years to optimize the trade-off among trapping efficiency, erase speed and retention performance. [11][12][13][14] Nevertheless, to ensure a good retention, the thin oxides composing the BE tunnel layer must have an excellent dielectric quality and a low density of traps. [8][9][10] On the other hand, the solution of a barrier engineered (BE) tunnel layer such as SiO 2 /Si 3 N 4 /SiO 2 (ONO), 11,12 which exploits the effect of different permittivity and band offsets of dielectric materials composing a multilayer, has been explored in the recent years.…”

“…[8][9][10] On the other hand, the solution of a barrier engineered (BE) tunnel layer such as SiO 2 /Si 3 N 4 /SiO 2 (ONO), 11,12 which exploits the effect of different permittivity and band offsets of dielectric materials composing a multilayer, has been explored in the recent years. 13,14 Besides, in the literature, post deposition annealing (PDA) treatments on the investigated oxide stacks at temperatures above 850 • C are rarely explored, and additionally a structural/chemical analysis is often missing. [11][12][13][14] Nevertheless, to ensure a good retention, the thin oxides composing the BE tunnel layer must have an excellent dielectric quality and a low density of traps.…”