Enhanced active‐feedback frequency compensation with on‐chip‐capacitor reduction feature for amplifiers with large capacitive load

Abstract

A large capacitive load amplifier with enhanced active-feedback frequency compensation is proposed in this paper. The enhancement is achieved through using a wide-bandwidth scalar circuit to increase the transconductance of the output stage so that the overall bandwidth of the amplifier can be extended considerably. Implemented in a standard CMOS 130-nm technology, with a supply of 0.7 V and consuming 27 μA of current, the amplifier drives a load capacitor of 15 nF. No on-chip resistor is needed; only a 0.91-pF compensation capacitor is used to maintain stability. The achieved gain-bandwidth product and phase margin are 1.28 MHz and 66.9°, respectively. Moreover, the slew rate is 0.263 V/μs. The active chip area is 0.0056 mm 2 . Figure 2. Frequency response: (a) the second gain stage with impedance adapting compensation and (b) proposed amplifier. GBW, gain-bandwith product. [Colour figure can be viewed at wileyonlinelibrary.com] 2122 M.W. LAU ET AL.

Dual loop cascode‐Miller compensation with damping factor control unit for three‐stage amplifiers driving ultralarge load capacitors

“…2,18 To this end, the compensation elements, R D and C C , should be related to g mL and C L of the final gain stage through 2,18 To this end, the compensation elements, R D and C C , should be related to g mL and C L of the final gain stage through…”

“…20 Instead of a single compensation loop used in many frequency compensation strategies such as CFCC, 15,16,18,[24][25][26][27][28][29][30][31] it contains two high-speed ac feedback loops for sensing the output voltage transients, in line with the circuit diagram shown in Figure 1F. 20 Instead of a single compensation loop used in many frequency compensation strategies such as CFCC, 15,16,18,[24][25][26][27][28][29][30][31] it contains two high-speed ac feedback loops for sensing the output voltage transients, in line with the circuit diagram shown in Figure 1F.…”

“…Simulation results of a DLCDFC prototype incorporating the new compensation strategy are addressed in section 3, to verify its advantages in terms of area and consuming power. 7,11,15,16,18,20 Furthermore, the compensation capacitors are now connected to the input of two current buffers with reduced input resistors of 1/g mC1 and 1/g mC2 , rather than the high-impedance v O1 node of the first stage output. The ac feedback loops along with the local damping factor control block all contribute to the proposed DLCDFC frequency compensation scheme, which differs in many ways from the previous frequency compensation schemes depicted in Figure 1.…”

“…Hybrid cascode feedforward compensation (HCFC) is, similarly, a modification of the CFCC scheme suited for three-stage amplifiers driving ultralarge load capacitors. 20 Instead of a single compensation loop used in many frequency compensation strategies such as CFCC, 15,16,18,[24][25][26][27][28][29][30][31] it contains two high-speed ac feedback loops for sensing the output voltage transients, in line with the circuit diagram shown in Figure 1F. The additional feedback loop increases further the complex poles frequency while requiring no additional power for implementation.…”

Global impedance attenuation network for multistage OTAs driving a broad range of load capacitor

“…High‐gain multistage amplifiers are preferred over single‐stage configurations in modern mixed‐signal processing modules with stringent accuracy requirement . These amplifiers ensure that maximum signal dynamic range is achieved under the low‐voltage supply of short‐channel metal‐oxide semiconductor (MOS) transistors since the output stage can be implemented by two transistors only.…”