Enhanced hot-electron performance of strained Si NMOS over unstrained Si

Kelly, D. Q.; Onsongo, D.; Dey, S.; Wise, R.; Cleavelin, R.; Banerjee, Soumen

doi:10.1109/relphy.2004.1315371

Cited by 4 publications

(2 citation statements)

References 13 publications

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“…These I D -V D curves were measured at |V GS-V t |=0.6V and 0.8V for n/pMOSFET. For the short channel, strained Si technology plus SiGe channel engineering is indeed significantly enhanced on drive current no matter what the MOSFET is, due to strained Si channel causing conduction band and valence band splitting which can reduce electronic inter-valley scattering [7] and hole inter-band scattering [8], therefore, reducing the carrier effective mass for hole carrier.…”

Section: Resultsmentioning

confidence: 99%

Si-capping thicknesses impacting compressive strained MOSFETs with temperature effect

Wang

Peng

Wang

et al. 2013

2013 International Symposium on Next-Generation Electronics

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Increasing the electrical performance of the MOSFETs with contact etch stop layer (CESL) and SiGe channel technologies in strain engineering is indeed approached. Using silicon capping layer performs the benefits on the smoothness of channel surface and the prevention of germanium penetration from SiGe layer. In this study, the deposited capping layer thicknesses with SiGe channel of (110) substrate wafer were 1.5 and 3.0 nm on the poly gate. The interesting device parameters including drive current, transconductance, threshold voltage (V T ) and subthreshold swing (S.S.) with temperature effect are systematically analyzed.

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Section: Resultsmentioning

confidence: 99%

Si-capping thicknesses impacting compressive strained MOSFETs with temperature effect

Wang

Peng

Wang

et al. 2013

2013 International Symposium on Next-Generation Electronics

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“…The slope of lifetime versus 1/V DS in the tensile-strained NMOS without the annealing is steeper than that in the control NMOS. This can be attributed to an increased Si-to-SiO 2 barrier height for electrons in the strained-Si devices, which is caused by the lowering of the conduction band in the strained Si [11]. The D 2 annealing increases the slope in both tensilestrained and control devices by which the maximum V DS , which guarantees a ten-year lifetime, increases.…”

Section: Characterization Of Annealing Effectmentioning

confidence: 99%

High-Pressure Deuterium Annealing Effect on Nanoscale Strained CMOS Devices

Cho

Lee

Chang

et al. 2008

IEEE Trans. Device Mater. Relib.

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High-pressure deuterium annealing was applied to nanoscale strained CMOS devices, and its effect was characterized in terms of charge pumping method, hot-carrier-induced stress, negative bias temperature instability stress, and 1/f noise for the first time. For the NMOS, the characteristics of both control and tensile-stressed NMOS devices were improved by annealing; in particular, tensile-stressed NMOS devices had more improved characteristics than the characteristics of control devices. However, for the PMOS, compressive-stressed PMOS devices particularly had more degraded characteristics compared with the characteristics of control PMOS devices.Index Terms-Charge pumping, CMOS, deuterium (D) annealing, high pressure, hot carrier stress, nanoscale, negative bias temperature instability (NBTI) stress, strained, 1/f noise.

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