Enhanced Redundant via Insertion with Multi-via Mechanisms

Chang, Ting-Feng; Kan, Tsang-Chi; Yang, Shih-Hsien; Ruan, Shanq-Jang

doi:10.1109/isvlsi.2011.50

Cited by 8 publications

(1 citation statement)

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“…In [15] the MWBM approach is particularly used to insert aligned stacked vias in a gridbased layout with up to three metal layers. Later on, Chang et al [4] introduced a new rectangle via candidate, which occupies a smaller footprint than a two via compound while it still prolongs via lifetime.…”

Section: Previous Workmentioning

confidence: 99%

Load-Aware Redundant Via Insertion for Electromigration Avoidance

Bigalke¹,

Lienig²

2016

Proceedings of the 2016 on International Symposium on Physical Design

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The ongoing shrinking of interconnects in integrated circuits (ICs) induces reliability issues caused by electromigration (EM), including void-induced failure mechanisms in IC vias. We propose a new post-routing approach to insert redundant vias specially targeted for EM avoidance. Our algorithm compares all possible insertions and utilizes the configuration with the highest reliability gain. This is achieved by considering the connecting segment loads. These loads are an estimation of the risk involved in creating EM-induced voids as a continuous function of current density, segment length and stress development over time. Inserting vias in those segments with highest loads, our approach efficiently increases circuit reliability by reducing EM effects. We were able to reduce the total, average and maximum via load for the MCNC benchmark suite on average by 6.6%, 4% and 13.9%, respectively. The increase in via reliability was confirmed by subsequent modeling of EM-inducing factors.

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Section: Previous Workmentioning

confidence: 99%