The ongoing shrinking of interconnects in integrated circuits (ICs) induces reliability issues caused by electromigration (EM), including void-induced failure mechanisms in IC vias. We propose a new post-routing approach to insert redundant vias specially targeted for EM avoidance. Our algorithm compares all possible insertions and utilizes the configuration with the highest reliability gain. This is achieved by considering the connecting segment loads. These loads are an estimation of the risk involved in creating EM-induced voids as a continuous function of current density, segment length and stress development over time. Inserting vias in those segments with highest loads, our approach efficiently increases circuit reliability by reducing EM effects. We were able to reduce the total, average and maximum via load for the MCNC benchmark suite on average by 6.6%, 4% and 13.9%, respectively. The increase in via reliability was confirmed by subsequent modeling of EM-inducing factors.

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Electromigration (EM) is becoming a progressively severe reliability challenge due to increased interconnect current densities. A shift from traditional (post-layout) EM veri cation to robust (pro-active) EM-aware design-where the circuit layout is designed with individual EM-robust solutions-is urgently needed. This tutorial will give an overview of EM and its e ects on the reliability of present and future integrated circuits (ICs). We introduce the physical EM process and present its speci c characteristics that can be a ected during physical design. Examples of EM countermeasures which are applied in today's commercial design ows are presented. We show how to improve the EM-robustness of metallization patterns and we also consider mission pro les to obtain application-oriented current-density limits. The increasing interaction of EM with thermal migration is investigated as well. We conclude with a discussion of application examples to shift from the current post-layout EM veri cation towards an EM-aware physical design process. Its methodologies, such as EM-aware routing, increase the EM-robustness of the layout with the overall goal of reducing the negative impact of EM on the circuit's reliability.

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