Exploring the use of the finite element method for electromigration analysis in future physical design

Thiele, Maik; Bigalke, Steve; Lienig, Jens

doi:10.1109/vlsi-soc.2017.8203466

Cited by 5 publications

(6 citation statements)

References 2 publications

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“…Figure 11 pictures the current-density distribution at the interface between the two patterns in a joint simulation; this is a measure of the error in the individual simulations. The maximum error is 3% in the visualized case; this is an acceptable value that has been verified for other patterns as well [24]. Verifying homogeneity of the current density at the cut surface between the two FEM submodels (the maximum deviation is 3% here) can be used to ensure that joint and separate simulations show matching results…”

Section: Simulation (Fem)mentioning

confidence: 52%

“…These simulations are only one part of the verification phase; they must be repeated iteratively in the design flow. For example, applying FEM for use in the full-chip verification of complex integrated circuits is far too slow [16,23,24].…”

Section: Efficient Fem For Em Analysismentioning

confidence: 99%

“…Layout Synthesis Figure 9: A full-chip EM simulation based on FEM should be uncoupled from the actual synthesis and verification process to compensate for the increasing circuit complexity. The resulting layout synthesis would then be restricted to preverified (routing) patterns to enable a fast pattern-based physical verification [24] An important prerequisite for the above-mentioned verification method of combining several discrete FEM simulations is that the partial solutions equate with the respective parts of the complete solution. This requirement is met if the boundary conditions are transformed correctly between the full and partition models, as we discuss next.…”

Section: Simulation (Fem)mentioning

confidence: 99%

“…Evaluating interconnect structures in advance and building the layout exclusively from evaluated structures enables much faster verification: even a single circuit simulation, i.e., generating the (simulated) library patterns and using them only once, can be faster than a conventional, complete FEM simulation of the entire final layout [24].…”

Section: Simulation (Fem)mentioning

confidence: 99%

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The Pressing Need for Electromigration-Aware Physical Design

Lienig¹,

Thiele²

2018

Proceedings of the 2018 International Symposium on Physical Design

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Electromigration (EM) is becoming a progressively intractable design challenge due to increased interconnect current densities. It has changed from something designers "should" think about to something they "must" think about, i.e., it is now a definite requirement. The ongoing IC-down-scaling is producing physical designs with ever-smaller feature sizes, which can easily lead to current densities that exceed their maximum allowable values. This invited talk introduces the fundamentals of EM, its interactions with thermal and stress migration, and presents appropriate modelling and simulation methodologies. Following a summary of EM-inhibiting effects in physical design, we propose ways of facilitating EM-compliant layout design in future technology nodes. CCS CONCEPTS • Hardware → Physical verification • Hardware → Electronic design automation → Methodologies for EDA

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Section: Simulation (Fem)mentioning

confidence: 52%

Section: Efficient Fem For Em Analysismentioning

confidence: 99%

Section: Simulation (Fem)mentioning

confidence: 99%

Section: Simulation (Fem)mentioning

confidence: 99%

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The Pressing Need for Electromigration-Aware Physical Design

Lienig¹,

Thiele²

2018

Proceedings of the 2018 International Symposium on Physical Design

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“…FEM-based verification will only be usable in the future if we achieve a significant reduction in simulation time. To meet this demand, we proposed in [5] a new methodology that reduces simulation time at least tenfold by using FEM for pre-layout pattern analysis without accuracy loss.…”

Section: Model Layoutmentioning

confidence: 99%

Electromigration Analysis of VLSI Circuits Using the Finite Element Method

Thiele

Bigalke

Lienig

2019

VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things

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Addressing electromigration (EM) during physical design has become crucial to ensure reliable integrated circuits. Simulation methods, such as the finite element method (FEM), are increasingly overwhelmed by the complexity of the task. With further technology scaling, it is predicted that FEM will not be usable anymore for a full-chip EM analysis due to complexity reasons. To address this bottleneck, we present a new methodology enabling an FEM-based full-chip EM analysis for future technologies down to 10 nanometer feature sizes. Our solution reduces analysis costs significantly by establishing pre-validated layout patterns without losing accuracy of the verification results. We thoroughly evaluate the necessary pattern geometries, pattern library size and the calculation time savings. We show that a number of 10 to 20 different patterns is sufficient for generation and analysis of layouts provided that the same pitch is used for each metal layer. Our full-chip meta-model EM analysis allows speedups of at least 10X compared to current FEM-based verification methods.

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Fundamentals of Electromigration

Lienig¹,

Thiele²

2018

Fundamentals of Electromigration-Aware Integrated Circuit Design

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Exploring the use of the finite element method for electromigration analysis in future physical design

Cited by 5 publications

References 2 publications

The Pressing Need for Electromigration-Aware Physical Design

The Pressing Need for Electromigration-Aware Physical Design

Electromigration Analysis of VLSI Circuits Using the Finite Element Method

Fundamentals of Electromigration

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