2007
DOI: 10.1109/led.2007.906084
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Enhanced Thermal Efficiency in Phase-Change Memory Cell by Double GST Thermally Confined Structure

Abstract: A novel phase-change memory cell with a doubleconfinement structure was proposed and fabricated in this work. By having an additional bottom Ge 2 Sb 2 Te 5 layer under the electrically confined active region, the heat loss can be effectively prevented. The temperature uniformity over the active region significantly improves and so does the thermal efficiency. Therefore, a low I RESET of about 0.3 mA and a reset power can be achieved. For the SET performance, a pulsewidth as low as 200 ns can be used without co… Show more

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Cited by 22 publications
(10 citation statements)
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“…For the total programming power shown in the inset, this stronger dependence is cancelled by the inverse relationship with the electrical cell resistance, and all curves fall roughly on the same trend. Although our default material parameter set is somewhat generic, and not fit to any particular test structure, the confined GST cells of [12] and [19] demonstrate a very similar trend to our model when L NW is fixed [symbols in Fig. 3(a)].…”
Section: Sensitivity Analysis and Discussionmentioning
confidence: 91%
See 1 more Smart Citation
“…For the total programming power shown in the inset, this stronger dependence is cancelled by the inverse relationship with the electrical cell resistance, and all curves fall roughly on the same trend. Although our default material parameter set is somewhat generic, and not fit to any particular test structure, the confined GST cells of [12] and [19] demonstrate a very similar trend to our model when L NW is fixed [symbols in Fig. 3(a)].…”
Section: Sensitivity Analysis and Discussionmentioning
confidence: 91%
“…We include TBR at material interfaces, and the model enables the calculation of the RESET current and the exact location of the peak temperature in a device without a priori assumptions about the latter. In particular, we focus on the nanopore-like [12], [13], [19] or nanowire (NW) [14], [15] device layout, which is thought to exhibit the best thermal confinement, and take advantage of the cylindrical symmetry for efficient modeling. We benchmark our compact model with FE simulations in both steady-state and transient (nanosecond time scale) conditions.…”
Section: Introductionmentioning
confidence: 99%
“…26 The low thermal conductivity of crystalline GST 27 can minimize the heat losses and, therefore, achieve the low RESET current and writing power. 28 Moreover, GST can be used as a thermoelectric heater and thermal barrier to improve the memory performance. 29,30 However, low-voltage programming adversely affects the retention characteristics of chalcogenide-based CBRAM devices, giving rise to the voltage-time dilemma.…”
Section: Introductionmentioning
confidence: 99%
“…Porelike [217] Partial confined [218] Phase change line [163] Phase change bridge [51] Dash-type [219] Phase change dash [43] 3D Xpoint [17] Moreover, optimizations of the heater material itself and thickness are proven to allow a reduction of the operating current, leaving room for further improvements. The µ-trench architecture has been integrated in a 90-nm 128-Mb array with programming currents of 0.3 mA of the storage element, which demonstrates the suitability of this structure for the production of high-density PCRAM arrays.…”
Section: Volumeminimizedmentioning
confidence: 99%