Enumeration technique in very large‐scale integration fixed‐outline floorplanning

Abstract

Even though enumeration is a common technique adapted in very large-scale integration (VLSI) floorplanning, its impact in terms of wirelength, whitespace, as well as runtime on the floorplanning has never been investigated comprehensively. In this study, enumerative floorplanner (EFP) is proposed here by using enumeration. The impact of the maximum enumeration order on VLSI floorplan layout is investigated and the tradeoff relationship with the wirelength, area and runtime is analysed as well. In EFP, dynamic programming enumerative clustering (DEC) technique is employed to reduce the worst-case time complexity and runtime. DEC also introduces the same number of possible permutations of modules while reducing the redundancy created in enumerative clustering (EC) without the usage of dynamic programming. A straightforward cost function is adapted to assist DEC to select the best cluster permutation, and a rigorous local refinement is proposed to compensate the EC's impact on the floorplan wirelength. Experimental results show that EFP is a high performance floorplanner when compared to existing methods in terms of robustness, scalability and stability.

An Improved Simulated Annealing Algorithm With Excessive Length Penalty for Fixed-Outline Floorplanning

“…As the fixed-outline floorplanning problem is becoming more practical, various algorithms have been proposed in the previous works. Hoo et al in [4] proposed a dynamic programming enumeration clustering method to decrease the worse case of time complexity and running time. In [5], the authors presented a novel algorithm, which starts with a sub-example of the prescribed floorplan and augments until a candidate solution is obtained.…”

“…1: the operation number n on B*-tree is set to 0 at the beginning; 2: the uphill number of accepting poor solution and the number of rejecting poor solution are initialized to 0; 3: empty list L; 4 if ≤ 0 then 11:…”

Constraint propagation in physical design of circuits

“…Physical design automation has become an active and successful research domain for decades. The tremendous and continuous challenge requires state‐of‐the‐art algorithms to facilitate the optimisation process [4, 5]. In a modern physical design, floorplanning, partitioning, placement, routing, and verification are proceeded recursively in a top‐down strategy.…”