Envelope and phase path recombination in ADPLL-based wideband polar transmitters

Syllaios, I.L.; Balsara, Poras T.; Staszewski, Robert Bogdan

doi:10.1109/dcas.2008.4695931

Cited by 4 publications

(4 citation statements)

References 6 publications

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“…For example, if x n is a ramp, then y n is constant, and the CT integrator input is an array of equally weighted impulses-so that its output is a uniform staircase function. 4 With timing errors, δ n = 0, and the treads of the staircase are either too brief or too long. In the context of the ADPLL, the treads are the output oscillation frequencies, whose widths are modulated by the jitter.…”

Section: Modelsmentioning

confidence: 99%

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Effect of Reference Clock Jitter and Demonstration of Near Image-Free Operation for the ADPLL

Ballantyne¹,

Geng

2010

IEEE Trans. Circuits Syst. II

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The effect of reference clock jitter on the alldigital phase-locked loop (ADPLL) is considered. The analog-todigital interface [e.g., a time-to-digital converter (TDC)] is considered only briefly. For the digital-to-analog interface [e.g., a digitally controlled oscillator (DCO)], the analysis is studied in detail. The power spectral density and the integrated power of the ADPLL's output phase noise are assessed for two types of reference clock jitter: 1) small correlated jitter (such as for a typical reference oscillator) and 2) uncorrelated jitter. Uncorrelated clock jitter (intentionally added at the DCO), which is uniformly spread over a sampling interval, is shown to nearly remove the digital images at the ADPLL output, which significantly lowers the minimum reference clock frequency in wireless designs.

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Section: Modelsmentioning

confidence: 99%

“…Where, for the ADPLL, H is as per(4) 6. The definitions of the various characteristic functions employed appear in (14), (15), and (18) 7.…”

mentioning

confidence: 99%

Effect of Reference Clock Jitter and Demonstration of Near Image-Free Operation for the ADPLL

Ballantyne¹,

Geng

2010

IEEE Trans. Circuits Syst. II

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“…Gierkink's [29] and Maffezzoni and Levantino's [30] continuous-time PN models (for N > 10) consider the ILO's cyclostationary nature and are accurate for any β, but they do not consider the reference PN itself. A multirate discrete-time model [36], [37] (for any N) applied in [31] accounts for the ILO's PN contribution from the reference, oscillator, and oscillator's PN folding but is only limited to the ideal IL (i.e., β = 1, similar as in [23]).…”

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confidence: 99%

A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking

Chen

Siriburanon

et al. 2022

IEEE J. Solid-State Circuits

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This article presents a millimeter-wave (mmW) frequency synthesizer based on a new charge-sharing locking (CSL) technique. A charge-preset capacitor is introduced for charge sharing with a resonant LC-tank for phase correction, while the resulting charge residue on the sharing capacitor is processed by a digital frequency-tracking loop (FTL) against the process, voltage, and temperature (PVT) variations. Furthermore, a general phase noise (PN) theory of CSL, with injection locking (IL) being a special case, is proposed based on a unified multirate z-domain model, supporting any frequency division ratio N and CSL (or IL) strength β. The new theory sheds light not only on all IL-like PN phenomena (chiefly, its "loop" bandwidth being up to half of the reference frequency, and the oscillator PN increasing 3 dB beyond the "loop" cutoff frequency) but also on how to choose the CSL bandwidth via the sharing capacitor in order to optimize the rms jitter performance. The prototype in 28-nm CMOS achieves 77-fs rms jitter in 21.75-26.25 GHz while consuming 16.5 mW for mmW quadrature frequency generation.

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“…Moreover, both the time resolution of the time-to-digital converter and the digitalcontrolled oscillator gain are sensitive PVT parameters since they are related to the minimum inverter delay and affected by the nonlinear varactor gain, respectively [9]- [12].…”

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confidence: 99%

Self-Calibrated Two-Point Delta–Sigma Modulation Technique for RF Transmitters

Lee

Park

et al. 2010

IEEE Trans. Microwave Theory Techn.

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A self-calibrated two-point delta-sigma modulation technique for CMOS RF transmitter is proposed. This calibration technique employs voltage-controlled oscillator (VCO) and delta-sigma modulator input ports in a frequency synthesizer. By monitoring the control voltage of a loop filter, the gain mismatch between two paths can be detected and completely calibrated by modifying the gain of the VCO path. The acceptable timing mismatch between the two paths is also investigated so that the timing can be controlled to ensure stable output performance. As a result, the phase modulation guarantees a robust performance against PVT variations without using any predistortion techniques. This technique is applied to a quad-band (850/900/1800/1900) GSM/EDGE transmitter for verification. For the amplitude modulation of the EDGE mode, a dc calibration is adopted to suppress unwanted carrier leakage tones. The measurement results show satisfactory GSM/EDGE spectrums and error vector magnitude performance at both low-and high-frequency bands.

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Envelope and phase path recombination in ADPLL-based wideband polar transmitters

Cited by 4 publications

References 6 publications

Effect of Reference Clock Jitter and Demonstration of Near Image-Free Operation for the ADPLL

Effect of Reference Clock Jitter and Demonstration of Near Image-Free Operation for the ADPLL

A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking

Self-Calibrated Two-Point Delta–Sigma Modulation Technique for RF Transmitters

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