Epilayer Optimization of NPN SiGe HBT with n+ Buried Layer Compatible With Fully Depleted SOI CMOS Technology

Misra, Prasanna Kumar; Qureshi, S.

doi:10.5573/jsts.2014.14.3.274

Cited by 4 publications

(1 citation statement)

References 42 publications

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“…[6] has Journal of Applied Mathematics and Physics been proved that reducing the width of the emitter can greatly improve the frequency of SiGe HBT. In addition, the band structure of silicon can be changed by introducing global strain or local strain to improve carrier mobility has been reported [7] [8]. Scholars have improved the performance of SiGe HBT by using stacked metal interconnect structures or introducing mechanical stress [9] [10].…”

Section: Introductionmentioning

confidence: 99%

Design and Simulation of Improved SOI SiGe Hetero-Junction Bipolar Transistor Architecture with Strain Engineering

Miao¹,

Li²,

Wen³

et al. 2020

JAMP

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In order to improve the electrical and frequency characteristics of SiGe heterojunction bipolar transistors (HBTs), a novel structure of SOI SiGe heterojunction bipolar transistor is designed in this work. Compared with traditional SOI SiGe HBT, the proposed device structure has smaller window widths of emitter and collector areas. Under the act of additional uniaxial stress induced by Si 0.85 Ge 0.15 , all the collector region, base region and emitter region are strained, which is beneficial to improve the performance of SiGe HBTs. Employing the SILVACO  TCAD tools, the numerical simulation results show that the maximum current gain β max , the Earley voltage V A are achieved for 1062 and 186 V, respectively, the product of β and V A , i.e., β × V A , is 1.975 × 10 5 V and, the peak cutoff frequency f T is 419 GHz when the Ge component in the base has configured to be a trapezoidal distribution. The proposed SOI SiGe HBT architecture has a 52.9% improvement in cutoff frequency f T compared to the conventional SOI SiGe HBTs.

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Section: Introductionmentioning

confidence: 99%

Design and Simulation of Improved SOI SiGe Hetero-Junction Bipolar Transistor Architecture with Strain Engineering

Miao¹,

Li²,

Wen³

et al. 2020

JAMP

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show abstract

A technique for simultaneously improving the product of cutoff frequency–breakdown voltage and thermal stability of SOI SiGe HBT

Zhang

Jin

et al. 2016

Chinese Phys. B

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The product of the cutoff frequency and breakdown voltage ( f T ×BV CEO ) is an important figure of merit (FOM) to characterize overall performance of heterojunction bipolar transistor (HBT). In this paper, an approach to introducing a thin N + -buried layer into N collector region in silicon-on-insulator (SOI) SiGe HBT to simultaneously improve the FOM of f T ×BV CEO and thermal stability is presented by using two-dimensional (2D) numerical simulation through SILVACO device simulator. Firstly, in order to show some disadvantages of the introduction of SOI structure, the effects of SOI insulation layer thickness (T BOX ) on f T , BV CEO , and the FOM of f T ×BV CEO are presented. The introduction of SOI structure remarkably reduces the electron concentration in collector region near SOI substrate insulation layer, obviously reduces f T , slightly increases BV CEO to some extent, but ultimately degrades the FOM of f T ×BV CEO . Although the f T , BV CEO , and the FOM of f T ×BV CEO can be improved by increasing SOI insulator SiO 2 layer thickness T BOX in SOI structure, the device temperature and collector current are increased due to lower thermal conductivity of SiO 2 layer, as a result, the self-heating effect of the device is enhanced, and the thermal stability of the device is degraded. Secondly, in order to alleviate the foregoing problem of low electron concentration in collector region near SOI insulation layer and the thermal stability resulting from thick T BOX , a thin N + -buried layer is introduced into collector region to not only improve the FOM of f T ×BV CEO , but also weaken the self-heating effect of the device, thus improving the thermal stability of the device. Furthermore, the effect of the location of the thin N + -buried layer in collector region is investigated in detail. The result show that the FOM of f T ×BV CEO is improved and the device temperature decreases as the N + -buried layer shifts toward SOI substrate insulation layer. The approach to introducing a thin N + -buried layer into collector region provides an effective method to improve SOI SiGe HBT overall performance.

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Novel Design of SOI SiGe HBTs with High Johnson's Figure-of-Merit

Wang

Jin

Zhang

et al. 2018

2018 IEEE 3rd International Conference on Integrated Circuits and Microsystems (ICICM)

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Epilayer Optimization of NPN SiGe HBT with n+ Buried Layer Compatible With Fully Depleted SOI CMOS Technology

Cited by 4 publications

References 42 publications

Design and Simulation of Improved SOI SiGe Hetero-Junction Bipolar Transistor Architecture with Strain Engineering

Design and Simulation of Improved SOI SiGe Hetero-Junction Bipolar Transistor Architecture with Strain Engineering

A technique for simultaneously improving the product of cutoff frequency–breakdown voltage and thermal stability of SOI SiGe HBT

Novel Design of SOI SiGe HBTs with High Johnson's Figure-of-Merit

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