Epitaxial growth of CdTe on (211) silicon mesas formed by deep reactive ion etching

Smith

et al. 2010

Journal of Elec Materi

HgCdTe heteroepitaxy on low-cost, large-lattice-mismatched substrates such as Si continue to be plagued by large threading dislocation densities that ultimately reduce the operability of the thermal imaging detector array. Molecular-beam epitaxy (MBE) of 10 lm-to 15 lm-thick CdTe buffer layers has played a crucial role in reducing dislocation densities to current state-ofthe-art levels. Herein, we examine the possibility that growth on locally backthinned substrates could prove advantageous in further reducing dislocation densities in the CdTe/Si heteroepitaxial system. Using defect decoration techniques, a decrease in dislocation (etch-pit) density of up to $42% has been measured in CdTe regions where the underlying Si substrate was chemically back-thinned to $20 lm. A theoretical understanding is proposed, where a substrate-thickness-dependent dislocation image force is a likely cause for the experimentally observed reduction in threading dislocation density. These observations raise the prospect of combining localized substrate thinning with other techniques to further reduce dislocation densities to levels sought for HgCdTe/CdTe/Si and other large-lattice-mismatched systems.

Section: Introductionmentioning

confidence: 95%

Feasibility of Localized Substrate Thinning for Reduced Dislocation Density in CdTe/Si Heterostructures

Smith

et al. 2010

Journal of Elec Materi

“…Several novel approaches have been attempted to reduce this density in CdTe buffer layers, including epitaxial lateral overgrowth, wafer bonding and layer transfer, and CdTe epitaxy on patterned substrates. [13][14][15] Additionally, Jacobs et al attempted growth of CdTe buffer layers on back-thinned conformal Si substrates. 16 It was reported that (211) Si substrates were locally backthinned by chemical etching, using a mixture of HF and HNO 3, down to thicknesses as low as 20 lm.…”

Section: Introductionmentioning

confidence: 99%

Si Wafer Thinning Techniques Compatible With Epitaxy of CdTe Buffer Layers

Smith

et al. 2011

Journal of Elec Materi

Reduction of threading dislocation density is critical for improving the performance of HgCdTe detectors on lattice-mismatched alternative substrates such as Si. CdTe buffer layers grown by molecular beam epitaxy (MBE), with thicknesses on the order of 8 lm to 12 lm, have helped reduce dislocation densities in HgCdTe layers. In this study, the reduction of threading dislocation densities in CdTe buffer layers grown on locally thinned Si substrates was examined. A novel Si back-thinning technique was developed that maintained an epiready front surface and achieved Si thicknesses as low as 1.9 lm. Threading dislocation densities, acquired by defect decoration techniques, were reduced by as much as 60% for CdTe buffer layers grown on these thinned regions when compared with unthinned regions. However, this reduction is inconsistent with prior notions that threading dislocation propagation is dominated by image forces. Instead, the thickness gradient of thinned Si may play a larger role.

Localized dry-etch substrate thinning for dislocation reduction in heteroepitaxial CdTe/Si(211)

Journal of Vacuum Science &Amp; Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phen

Nozaki

et al. 2011

Threading dislocations are a significant problem for heteroepitaxial growth of thin films on large lattice-mismatched substrates. In the case of HgCdTe thin films on Si, Ge, or GaAs, the molecular beam epitaxy (MBE) of 10–15-μm-thick CdTe buffer layers has historically played a crucial role in reducing threading dislocation densities to current state-of-the-art levels. In this work, the authors investigate a localized substrate thinning approach and its overall effect on further reducing dislocation densities in the CdTe/Si heteroepitaxial system. In using substrates with regions thinned to thicknesses on the order of the CdTe buffer, the attempt is to reduce the dislocation image force acting from the interface toward the epilayer surface. The authors employ both wet- and dry-etching techniques to create locally back-thinned regions of Si(211) wafers. Localized rather than whole wafer thinning was necessary to maintain sufficient substrate thickness for handling. The opposite sides of the wafers were cleaned using standard techniques prior to CdTe MBE. Scanning electron microscopy and Fourier transform infrared spectroscopy were used to measure epilayer and substrate thicknesses. Using CdTe defect-decoration techniques, a decrease in threading dislocation density by up to 60% has been observed in regions for which the underlying Si substrate was thinned to 2 μm. Results obtained for wet-etch and dry-etch back-thinning approaches suggest that the dislocation-reduction mechanism is not solely based on substrate-thickness induced image forces.