Error Floor Estimation of Long LDPC Codes on Partial Response Channels

Abstract

The presence of error floor in low density parity check (LDPC) codes is of great concern for potential applications of LDPC codes to data storage channels, which require the error correcting code (ECC) to maintain the near-capacity error correcting performance at frame error rate as low as 10 −12 . In order to investigate the error floor of LDPC codes under partial response channels used in data storage systems, we propose a new estimation method combining analytical tools and simulation, based on the concept of trapping sets. The definition of trapping sets is based on the dominant error patterns observed in the decoding process. The goal is to accurately estimate the error rate in the error floor region for certain types of LDPC codes under the partial response channel and further extend the frame error rate down to 10 −14 or lower. Towards this goal, we first use field programmable gate array (FPGA) hardware simulation to find the trapping sets that cause the decoding failure in the error floor region. For each trapping set, we extract the parameters which are key to the decoding failure rate caused by this trapping set. Then we use a much simpler in situ hardware simulation with these parameters to obtain the conditional decoding failure rate. By considering all the trapping sets we find, we obtain the overall frame error rate in the error floor region. The estimation results for a length-4623 QC-LDPC code under the EPR4 channel are within 0.3 dB of the direct simulation results. In addition, this method allows us to estimate the frame error rate of a LDPC code down to 10 −14 or lower.

Concatenated Low-Density Parity-Check and BCH Coding System for Magnetic Recording Read Channel With 4 kB Sector Format

“…Using high-speed hardware simulators based on FPGA (field programmable gate array) devices, recent work [8]- [13] has empirically investigated the performance of LDPC codes. In particular, the authors of [12] developed a simulation-assisted method to estimate the LDPC decoding performance down to and lower under ideal PR channel with Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. AWGN noise only, which has been empirically verified down to the SER of using FPGA-based simulation.…”

Modelling and characterization of NAND flash memory channels

“…On the other hand, advanced soft decision-based error correction codes (ECC) such as low density parity check codes (LDPC) [1,2,3] are gradually replacing traditional ECC using hard decisions in the current flash memory design practice in order to compensate for the high raw bit error probability. Decoding of these soft decision-based algorithms depends heavily on the accuracy of the reliability information obtained by multiple memory measurements, or a channel model with exactly characterized threshold voltage distribution.…”

Performance Enhancement of High Order LDPC Coded Modulation Systems with Application in Mobile Backhaul Networks

“…Based on the premise that the EF of a given LDPC code is an artifact of its underling TS structures, several approaches have evolved to use the IS technique and variations thereof to efficiently predict these EFs for various channel conditions and TS structures, see e.g., [29,[69][70][71][72][73][74][75]. For instance, in [69] an AWGN channel is considered and a method for identifying the error boundary of the decoder for a given TS is proposed.…”

“…Other applications of IS for evaluating the EF of the LDPC codes in AWGN channels are based on shifting the mean of the noise distribution to induce more frequent errors in the TSs without considering a deterministic error boundary, e.g., [29,73,75]. In addition to AWGN channels, this approach is also adopted to evaluate the EF performance of the LDPC codes for other channel models, e.g., the partial response channel [70], and the magnetic recording channel [71]. The application of IS scheme has also been extended to the case of non-binary LDPC codes in [76].…”