ESD protection design and enhancement in the power 60‐V n‐channel LDMOS by embedded‐SCR anode islands

Abstract

An electrostatic discharge (ESD) strengthening design of high-voltage (HV) n-channel laterally diffused metal-oxide semiconductor (nLDMOS) transistors combined with embedded-SCR anode islands is investigated. After a systematic layout implementation and analysis, the anti-ESD robustness [or secondary breakdown current (I t2)] of drain pnp-arranged and SCR isolated-type DUTs were higher than 7-A (ESD reliability improvements of these nLDMOS-SCR devices were more than 282.5% (199.2%) higher than that of the pure nLDMOS (pnp-stripe) component. Also, it can be found that the ESD robustness of the pnp-arranged type is greater than the npnarrangement. Therefore, an adequate architecture of an HV nLDMOS device embedded with an SCR (pnp-arranged) and SCR isolated manner can gain high ESD-reliability immunity.