Influence of Latch-Up Immunity Structure on ESD Robustness of SOI-LIGBT Used As Output Device

Ye, Ran; Liu, Siyang; Tian, Yu‐Ping; Yang, Xue; Sun, Weifeng; Su, Wei; Lin, Feng; Sun, Guang–Zhen; Ma, Shulang; Liu, Yuwei

doi:10.1109/tdmr.2018.2829550

Cited by 5 publications

(3 citation statements)

References 20 publications

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“…They both operate via a double-injection mechanism and have excellent current density based on the latch-mode operation of NPN and PNP parasitic bipolar transistors. Consequently, several engineers select the SCR and LIGBT as high-voltage ESD protection devices, and various studies have been conducted to optimize their electrical characteristics [15]- [17]. However, because the critical electric field (E C ) is significantly high compared to the forward voltage drop in 4H-SiC, a strong snapback phenomenon occurs [18], [19].…”

Section: Introductionmentioning

confidence: 99%

“…Although the two traditional devices have a relatively wide range of snapback characteristics, they have excellent current-driving capability. Therefore, various studies have been conducted in a silicon environment to utilize them actively [14]- [17]. However, when these devices are fabricated using the 4H-SiC materials, the difference between the trigger voltage (V t1 ) and holding voltage (V h ) becomes even larger.…”

Section: Introductionmentioning

confidence: 99%

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4H-SiC-Based ESD Protection Design With Optimization of Segmented LIGBT for High-Voltage Applications

Jin

Lee

et al. 2021

IEEE J. Electron Devices Soc.

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4H-SiC is a wide-bandgap material that exhibits excellent high-temperature conductivity and high operating voltage. These characteristics can provide high electrostatic discharge (ESD) robustness in high voltage applications. However, a considerably wide range of snapback phenomena is triggered for 4H-SiC-based ESD protection devices owing to a high critical electric field. In this study, an ESD protection device based on a lateral insulated-gate bipolar transistor (LIGBT) with a new structure that creates an internal silicon-controlled rectifier (SCR) path is proposed. The proposed ESD protection device minimizes the effective base region of the NPN parasitic bipolar transistor to the gate length based on the internal SCR operation of the LIGBT. It also adjusts the emitter injection efficiency of the PNP parasitic bipolar transistor by introducing a segment topology and inserting an additional implant area. Consequently, the proposed ESD protection device significantly improves the wide range of snapback phenomena occurring in the 4H-SiC materials. A conventional SCR, the LIGBT, and the proposed protection device were fabricated using the 4H-SiC process under the same condition, and their electrical characteristics were comparatively analyzed using a transmission-line pulse system. Moreover, its high-temperature reliability was evaluated at 300-500 K to examine the compatibility with 4H-SiC devices and circuits that require a relatively high-temperature operation.INDEX TERMS Electrostatic discharge, holding voltage, snapback, silicon-controlled rectifier, lateral insulated-gate bipolar transistor.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

4H-SiC-Based ESD Protection Design With Optimization of Segmented LIGBT for High-Voltage Applications

Jin

Lee

et al. 2021

IEEE J. Electron Devices Soc.

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“…The W-type window can help achieve high current discharge capability and high robustness. In 2018, several antilatch-up structures based on SOI-LIGBT device were proposed and the relationship between anti-latch-up capability and robustness was analyzed [9,10] .…”

Section: Introductionmentioning

confidence: 99%

Design and analysis of a NMOS triggered LIGBT structure for electrostatic discharge protection

Cheng

Zhang

et al. 2019

J. Semicond.

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A novel NMOS triggered LIGBT (NTLIGBT) structure is proposed for electrostatic discharge (ESD) protection in this paper. The structure utilizes internal NMOS to trigger SCR-like structure in LIGBT. The trigger voltage is significantly reduced because the embedded NMOS causes N+-drain/P-body junction being apt to avalanche breakdown. At the same time, the new parasitic PNP transistor including the newly added P+-region as a collector forms another path to bleed ESD current and then the conductivity modulation in the LIGBT is weakened. As a result, the holding voltage is increased. So, the proposed NTLIGBT structure has a narrow ESD design window. The simulation results show an improvement of 71.5% in trigger voltage and over 50% in holding voltage comparing with the conventional LIGBT structure.

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Improved UHV IGBT−Cell for ESD Protection with High Holding Voltage via a 0.5µm BCD Process

Zhou

Chen

Lan

et al. 2021

2021 IEEE International Conference on Consumer Electronics-Taiwan (ICCE-TW)

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Influence of Latch-Up Immunity Structure on ESD Robustness of SOI-LIGBT Used As Output Device

Cited by 5 publications

References 20 publications

4H-SiC-Based ESD Protection Design With Optimization of Segmented LIGBT for High-Voltage Applications

4H-SiC-Based ESD Protection Design With Optimization of Segmented LIGBT for High-Voltage Applications

Design and analysis of a NMOS triggered LIGBT structure for electrostatic discharge protection

Improved UHV IGBT−Cell for ESD Protection with High Holding Voltage via a 0.5µm BCD Process

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