eSiGe Global and Micro Loading Effect Study in High Performance 45nm CMOS Technology

He, Yonggen; Tu, Huojin; Lin, Jing; Song, Hualong; Wang, Jun; Ma, Guiyin; Ye, Bin; Yu, Tzuchiang; Wu, Jingang

doi:10.1149/1.3567665

Cited by 4 publications

(2 citation statements)

References 7 publications

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“…After a dilute HF (100:1) clean and standard RCA clean to remove surface native oxide and particle, the blanket wafers processed with high temperature ISSG and RTON process respectively. The pattern wafers were processed through a state of art 45nm CMOS flow [4] as described in below. After active area definition by shallow trench isolation patterning and etch, different STI oxidation processed were done by ISSG and RTON, then followed with HARP oxide gap filling.…”

Section: Methodsmentioning

confidence: 99%

A Novel Shallow Trench Isolation Liner Dielectric to Enhance NMOS Performance toward 45nm and Beyond

Yu²,

et al. 2012

ECS Trans.

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In the present work, a novel RTON (Rapid Thermal Oxidation and Nitridation) was investigated as STI (Shallow Trench Isolation) liner dielectric in 45-nm CMOS. Compare with conventional ISSG (In-Situ Steam Generation) oxide, this RTON liner demonstrate better device performance for NMOS transistors both in long channel and short channel. It shown >4% Ioff/Ion improvement and exhibit more tighten SRAM standby leakage distribution. These performance gains can be explained by RTON liner contribution to NMOS channel tensile stress enhancement as well as its excellent capability to prevent channel doping diffusion.

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Section: Methodsmentioning

confidence: 99%

A Novel Shallow Trench Isolation Liner Dielectric to Enhance NMOS Performance toward 45nm and Beyond

Yu²,

et al. 2012

ECS Trans.

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“…The blanket wafer was processed with 1000~1100 o C hydrogen baking, and then followed by low temperature SiGe Epi. The pattern wafers were processed through a state of art 45nm CMOS flow as described in below [7]. After active area definition by shallow trench isolation, channel implants were used to determine device threshold voltage (Vth).…”

Section: Device Fabricationmentioning

confidence: 99%

Investigation of Intermittent Haze in 300mm SiGe Epitaxy Process and its Impact on PMOS Device Performance

et al. 2012

ECS Trans.

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One big challenge of epitaxy growth SiGe process is defect control. Many factors have impacts on SiGe film property, such as surface oxide remaining, surface damage of Si substrate post dry etch or wet etch, impurity of chamber ambient and etc. In this work, a special intermittent crater-like "haze" was discussed for surface characterization. It was found that haze happened intermittently and most likely tends to occur after tool idle over twenty hours. Furthermore the haze intensity trend down company with wafer seasoning. As a consequential result, the CMOS devices processed SiGe-epi under intermittent haze condition would result in performance degradation especially for junction leakage. Some countermeasures (or suggested solutions) to suppress this intermittent haze are proposed.

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Selective epitaxial growth of stepwise SiGe:B at the recessed sources and drains: A growth kinetics and strain distribution study

et al. 2016

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The selective epitaxial growth of Si1-xGex and the related strain properties were studied. Epitaxial Si1-xGex films were deposited on (100) and (110) orientation wafers and on patterned Si wafers with recessed source and drain structures via ultrahigh vacuum chemical vapor deposition using different growing steps and Ge concentrations. The stepwise process was split into more than 6 growing steps that ranged in thicknesses from a few to 120 nm in order to cover the wide stages of epitaxial growth. The growth rates of SiGe on the plane and patterned wafers were examined and a dependence on the surface orientation was identified. As the germanium concentration increased, defects were generated with thinner Si1-xGex growth. The defect generation was the result of the strain evolution which was examined for channel regions with a Si1-xGex source/drain (S/D) structure.

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eSiGe Global and Micro Loading Effect Study in High Performance 45nm CMOS Technology

Cited by 4 publications

References 7 publications

A Novel Shallow Trench Isolation Liner Dielectric to Enhance NMOS Performance toward 45nm and Beyond

A Novel Shallow Trench Isolation Liner Dielectric to Enhance NMOS Performance toward 45nm and Beyond

Investigation of Intermittent Haze in 300mm SiGe Epitaxy Process and its Impact on PMOS Device Performance

Selective epitaxial growth of stepwise SiGe:B at the recessed sources and drains: A growth kinetics and strain distribution study

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