Estimation during Design Phases of Suitable SRAM Cells for PUF Applications Using Separatrix and Mismatch Metrics

Alheyasat, A.; Torrens, Gabriel; Bota, S.; Alorda, B.

doi:10.3390/electronics10121479

Cited by 3 publications

(5 citation statements)

References 22 publications

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“…This simulation outcome clearly demonstrates that the proposed approach improves the randomness of the PUF output. The output randomness can be considered further based on predicting the output according to the threshold voltage mismatch from [28], which can be expressed as follows:…”

Section: Simulation Results Comparisonmentioning

confidence: 99%

A Reconfigurable SRAM CRP PUF with High Reliability and Randomness

Pham,

Ngo,

Nam

et al. 2024

Electronics

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This paper presents a novel reconfigurable SRAM CRP PUF that can achieve high reliability and randomness. In conventional reconfigurable SRAM CRP PUFs, imprecise timing control can produce a biased response output, which is typically attributed to mismatches in the connection of input control signals to the two inverter arrays in the layout floorplan. We propose a timing control scheme along with the addition of an adjunct NMOS transistor to address this issue. This eliminates the connection mismatches for the challenge and word-line inputs to the two inverter arrays. Furthermore, we employ symmetric layout techniques to achieve the randomness of response output. The symmetric arrangement of the two inverter arrays maximizes the inherent random output characteristics derived from process variation. The pre-charge input signal is symmetrically connected to each array to prevent delay mismatches. A 16 × 9-bit reconfigurable PUF array is fabricated by using a 180 nm CMOS process, with a PUF cell area of 1.2 × 104 F2/bit. The experimental results demonstrate an inter Hamming distance of 0.4949 across 40 chips and an intra Hamming distance of 0.0167 for a single chip in 5000 trials. The measured worst bit error rate (BER) is 4.86% at the nominal point (1.8 V, 25 °C). The proposed prototype exhibits good reliability and randomness, as well as a small silicon area when compared to the conventional SRAM CRP PUFs.

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Section: Simulation Results Comparisonmentioning

confidence: 99%

A Reconfigurable SRAM CRP PUF with High Reliability and Randomness

Pham,

Ngo,

Nam

et al. 2024

Electronics

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“…Results were 97.1% and 98.3% respectively, suggesting that the percentages of cells listed in Table 3, which as stated by [35] correspond to the least influenced by external disturbances, will be largely unaffected by these factors. These results are in line with those of [35,39].…”

mentioning

confidence: 83%

“…The greater the mismatch of a cell, the greater the distance from the point (0, 0) to the separatrix and, consequently, the greater the probability of the cell starting always at the same logic value [35].…”

Section: Cell Imbalance Factormentioning

confidence: 99%

“…This has been automated by means of a search algorithm using the Cadence Ocean scripting framework. The algorithm will try different starting points in the axis of interest, and determine the starting point with the minimum voltage that makes the cell start up to the opposite state it was biased to (flip its nominal start-up state) [35]. This is represented by blue trajectories in Figure 4b,c.…”

Section: Cell Imbalance Factormentioning

confidence: 99%

“…The considered temperature range was −20 • C to +60 • C and the start-up time was varied more than one order of magnitude according to [37,38]. Results were 97.1% and 98.3% respectively, suggesting that the percentages of cells listed in Table 3, which as stated by [35] correspond to the least influenced by external disturbances, will be largely unaffected by these factors. These results are in line with those of [35,39].…”

mentioning

confidence: 99%

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SRAM-Based PUF Reliability Prediction Using Cell-Imbalance Characterization in the State Space Diagram

et al. 2022

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This work proposes a methodology to estimate the statistical distribution of the probability that a 6T bit-cell starts up to a given logic value in SRAM memories for PUF applications. First, the distribution is obtained experimentally in a 65-nm CMOS device. As this distribution cannot be reproduced by electrical simulation, we explore the use of an alternative parameter defined as the distance between the origin and the separatrix in the bit-cell state space to quantify the mismatch of the cell. The resulting distribution of this parameter obtained from Monte Carlo simulations is then related to the start-up probability distribution using a two-component logistic function. The reported results show that the proposed imbalance factor is a good predictor for PUF-related reliability estimation with the advantage that can be applied at the early design stages.

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