Estimation of Iddq for early chip and technology design decisions

Hook, T.; Wissel, L.; Mazgaj, D.

doi:10.1109/cicc.2003.1249474

Cited by 6 publications

(2 citation statements)

References 5 publications

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“…A statistical OCV uplift factor is applied to leakage simulation to account for superlinear leakage dependence on gate length and other variation. [1] This is correlated to hardware measurement. Data mining of design statistics yields the composition of device Vts and channel lengths used in optimizing frequency and leakage.…”

Section: A Design Projectionsmentioning

confidence: 99%

Mobile CPU power/performance benchmarking and process technology co-optimization

Bucki

Bridges

Bowers

et al. 2014

2014 IEEE International Conference on IC Design &Amp; Technology

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The form factor of mobile devices and their associated thermal dissipation characteristics present practical limits to SoC (and specifically CPU) power consumption. Multiple maximum temperature constraints interact with the thermal "time constant" of package and product to limit allowable die temperature. This can constrain maximum CPU frequency in real use cases. The co-design of product and process technology is required to maximize thermally constrained performance. Technology features, device Ieff/Ioff setpoints, and circuit design styles are all levers to optimize thermally constrained performance. A methodology for early prediction of product sensitivities to these levers is required to enable their definition sufficiently early in the development cycle of the technology node.

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Section: A Design Projectionsmentioning

confidence: 99%

Mobile CPU power/performance benchmarking and process technology co-optimization

Bucki

Bridges

Bowers

et al. 2014

2014 IEEE International Conference on IC Design &Amp; Technology

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“…This allows the leakage to be accurately calculated at any process, voltage and temperature [4,5]. This method has been embedded in the IBM power models.…”

Section: A Chip Power Analysis Across Process Voltage and Temperaturementioning

confidence: 99%

Using selective voltage binning to maximize yield

Lichtensteiger

Bickford

2012

2012 SEMI Advanced Semiconductor Manufacturing Conference

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Yield loss associated with leakage screens is increasing as products migrate to technologies with thinner gate oxide and more aggressive lithography. Product competitiveness requires meeting low power and when products have exhausted design options, tighter than 3 sigma fast leakage screens are implemented to reduce power which can result in significant yield loss.Selective Voltage Binning (SVB) provides a way to interlock a lower operating voltage in the system with process window information so that faster parts can be run in the system at a lower voltage avoiding the yield loss associated with custom leakage screens

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