Understanding the reliability implications for siliconon-insulator (SOI) is crucial for its use in ULSI technology. The fabrication process of SO1 material and the device operation, due to the buried oxide (BOX) layer, could present additional concerns for meeting reliability requirements. In this paper, we discuss the reliability issues with silicon-on-insulator (SOI) technology. We focus on partially depleted (PD) SO1 CMOS technology using SIMOX and bonded substrate material. We compare the reliability mechanisms, namely channel hot electron (CHE), gate oxide time dependent dielectric breakdown (TDDB), bias temperature stress (BTS) and plasmainduced charging damage, to bulk CMOS. In addition, results from high performance microprocessors subjected to bum-in stress are presented. Finally, we discuss the circuitry implications for electrostatic discharge (ESD). Fig I . Due to the bipolar action, SO1 off-current is higher than bulk. This can limit the applied bum-in condition. Tsi = 170.0nm, Tbox = 350nm

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