Estimation of Simultaneous Switching Noise From Frequency-Domain Impedance Response of Resonant Power Distribution Networks

Kim, Woopoung

doi:10.1109/tcpmt.2011.2157503

Cited by 23 publications

(7 citation statements)

References 12 publications

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“…A successful PDN design requires the power/ground loops presenting acceptable impedances at all frequencies of interest. Many previous works focused on the worst voltage drop in time- [6], [7], [8] and in frequency-domain [9], [10], [11] Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored.…”

Section: Introductionmentioning

confidence: 99%

Worst-Case Noise Area Prediction of On-Chip Power Distribution Network

Zhang¹,

Liu

et al. 2014

Proceedings of SLIP (System Level Interconnect Prediction) on System Level Interconnect Prediction Workshop

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Abstract-We propose a prediction of the worst-case noise area of the supply voltage on the power distribution network (PDN). Previous works focus on the worst-peak droop to sign off PDN. In this work, we (1) study the behavior of circuit delay over the worst-area noise (2) study the worst-case noise area of a lumped PDN model (3) develop an algorithm to generate the worst-case current for general PDN cases (4) predict the longest delay of a datapath due to power integrity. Experimental results show that the worst-area noise induces additional delay than that of the worst-peak noise.

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Section: Introductionmentioning

confidence: 99%

Worst-Case Noise Area Prediction of On-Chip Power Distribution Network

Zhang¹,

Liu

et al. 2014

Proceedings of SLIP (System Level Interconnect Prediction) on System Level Interconnect Prediction Workshop

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“…Since advanced CMOS LSIs operate at higher clock frequencies and at lower supply voltage, power integrity design is becoming more critical to maintain digital electronic systems stable [1]- [2]. Especially, chip-package anti-resonance in the power distribution network (PDN) occurs due to the parallel combination of on-die capacitance and package inductance.…”

Section: Introductionmentioning

confidence: 99%

Q factor damping of anti-resonance peak by variable on-die capacitance

Ichimura

Kiyoshige

Terasaki

et al. 2014

2014 International Symposium on Electromagnetic Compatibility

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“…To estimate anti-resonance frequency and peak level exactly, design information of on-chip PDN is needed as well as package design information. A total PDN impedance which consisted of chip PDN, package PDN, and board PDN has become an important design parameter to stabilize the high-speed digital system operation [1]- [4]. Furthermore this antiresonance peak is normally difficult to observe directly by the conventional methods.…”

Section: Introductionmentioning

confidence: 99%

Power integrity improvement by controlling on-die PDN properties

Sudô

Kiyoshige

Ichimura

et al. 2013

2013 IEEE Electrical Design of Advanced Packaging Systems Symposium (EDAPS)

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Power integrity has became a serious issue in the advanced CMOS digital systems, because power supply noise must be suppressed to guarantee normal logic operation and its stability. Therefore, chip-package-board co-design has become important by taking into consideration the total impedance seen from the chip. Especially, parallel resonance peaks in the distribution network (PDN) due to the chip-package interaction induces the unwanted power supply fluctuation, and results in the degradation of signal integrity and electromagnetic interference (EMI).In this paper, three test chips were designed with different onchip PDN properties. The effects of critical damping condition for the total PDN impedance on power supply noise has been examined by adding different RC circuit to the intrinsic on-die RC circuit of chip. The measurement and analysis of power supply noises for the three test chips showed typical characteristics of oscillatory region and damped regions The critical damping condition against the anti-resonance peak has been proved to be effective to suppress the power supply noise on the chip.

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Estimation of Simultaneous Switching Noise From Frequency-Domain Impedance Response of Resonant Power Distribution Networks

Cited by 23 publications

References 12 publications

Worst-Case Noise Area Prediction of On-Chip Power Distribution Network

Worst-Case Noise Area Prediction of On-Chip Power Distribution Network

Q factor damping of anti-resonance peak by variable on-die capacitance

Power integrity improvement by controlling on-die PDN properties

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