EUV resist curing technique for LWR reduction and etch selectivity enhancement

Narishige, Kazuki; Katsunuma, Takayuki; Honda, Masashi; Yatsuda, Koichi

doi:10.1117/12.916340

Cited by 13 publications

(6 citation statements)

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“…When the H 2 plasma irradiation time was longer than 20 s, the ITO etch rate decreased and became constant at about 30 nm=min. The reason for the decrease in ITO etch rate is assumed to be the following: (a) Si was generated from the upper electrode and=or other chamber parts, 30) or (b) ITO surface densification=modification occurred after a long H 2 plasma exposure (>20 s). Specifically, excessive H 2 plasma exposure suppressed ITO etching owing to the generation of a protective surface layer.…”

Section: Resultsmentioning

confidence: 99%

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Cyclic etching of tin-doped indium oxide using hydrogen-induced modified layer

Hirata¹,

Fukasawa²,

Nagahata³

et al. 2018

Jpn. J. Appl. Phys.

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The rate of etching of tin-doped indium oxide (ITO) and the effects of a hydrogen-induced modified layer on cyclic, multistep thin-layer etching were investigated. It was found that ITO cyclic etching is possible by precisely controlling the hydrogen-induced modified layer. Highly selective etching of ITO/SiO 2 was also investigated, and it was suggested that cyclic etching by selective surface adsorption of Si can precisely control the etch rates of ITO and SiO 2 , resulting in an almost infinite selectivity for ITO over SiO 2 and in improved profile controllability.

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Section: Resultsmentioning

confidence: 99%

“…In this study, we intentionally controlled the amount of Si generated from the upper electrode, 30) and demonstrate the highly selective cyclic etching. Figure 6 shows the dependence of the amounts of etched ITO and SiO 2 on Ar exposure time.…”

Section: Highly Selective Cyclic Etching Over Mask Materialsmentioning

confidence: 99%

Cyclic etching of tin-doped indium oxide using hydrogen-induced modified layer

Hirata¹,

Fukasawa²,

Nagahata³

et al. 2018

Jpn. J. Appl. Phys.

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“…However, that is probably not a major problem because we have powerful resist smoothing technology. [8][9] On the other hand, we present an example in which a difference in the design of the carbon block pattern, which comprises resist and BARC, has a large influence when the pattern is placed above an SiO2 spacer.…”

Section: -1 Block Scheme Comparisonmentioning

confidence: 98%

Sustainability and applicability of spacer-related patterning towards 7nm node

Oyama

Yamauchi

Hara

et al. 2015

Advances in Patterning Materials and Processes XXXII

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Self-aligned multiple patterning technique has enabled the further down scaling through 193 immersion lithography extension [1][2][3][4][5]. In particular, focus on the logic device scaling, we have finished the verification of patterning technology of up to 10nm node [6-7], we will discuss about some patterning technologies that are required to 7nm node. For critical layers in FinFET devices that presume a 1D cell design, there is also a need not just for the scaling of grating patterns but also for pattern cutting process. In 7nm node, cutting number increase in metal or fin layer, and also pattern splitting of contact or via is complicated, so both cost reduction and process controllability including EPE are strongly required. For example, inverse hardmask scheme in metal layer can improve CD variation of the Cu wiring. Furthermore hole pattern shrink technology in contact layer, by the combination with the exposure technique which has k1 0.25 or less, can achieve both cost reduction and reducing the numbers of pitch splitting. This paper presents the possibility of immersion-based multiple patterning techniques for up to 7nm node.

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“…Previously published data by Honda et al characterized the depth of the of e-beam penetration into a typical organic matrix to be well over 100nm at typical DCS plasma conditions 13,14 . It then ,.s , , TL Open TL Open + Depo TL Open + 2x Depo becomes apparent that with scaled resist, TL and planarizer thicknesses, the ballistic electrons can penetrate well into the planarizer stack to provide enhanced mechanical resistance to the stress induced deformation previously observed during the oxide etch.…”

Section: Oood Trarsformentioning

confidence: 98%

Trench and hole patterning with EUV resists using dual frequency capacitively coupled plasma (CCP)

et al. 2015

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Patterning at 10 nm and sub-10 nm technology nodes is one of the key challenges for the semiconductor industry. Several patterning techniques are under investigation to enable the aggressive pitch requirements demanded by the logic technologies. EUV based patterning is being considered as a serious candidate for the sub-10nm nodes. As has been widely published, a new technology like EUV has its share of challenges. One of the main concerns with EUV resists is that it tends to have a lower etch selectivity and worse LER/LWR than traditional 193nm resists. Consequently the characteristics of the dry etching process play an increasingly important role in defining the outcome of the patterning process.In this paper, we will demonstrate the role of the dual-frequency Capacitively Coupled Plasma (CCP) in the EUV patterning process with regards to improving LER/LWR, resist selectivity and CD tunability for holes and line patterns. One of the key knobs utilized here to improve LER and LWR, involves superimposing a negative DC voltage in RF plasma at one of the electrodes. The emission of ballistic electrons, in concert with the plasma chemistry, has shown to improve LER and LWR. Results from this study along with traditional plasma curing methods will be presented. In addition to this challenge, it is important to understand the parameters needed to influence CD tunability and improve resist selectivity. Data will be presented from a systematic study that shows the role of various plasma etch parameters that influence the key patterning metrics of CD, resist selectivity and LER/LWR. This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities.

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EUV resist curing technique for LWR reduction and etch selectivity enhancement

Cited by 13 publications

References 0 publications

Cyclic etching of tin-doped indium oxide using hydrogen-induced modified layer

Cyclic etching of tin-doped indium oxide using hydrogen-induced modified layer

Sustainability and applicability of spacer-related patterning towards 7nm node

Trench and hole patterning with EUV resists using dual frequency capacitively coupled plasma (CCP)

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