Evaluating the Impact of Resistive Defects on FinFET-Based SRAMs

Copetti, T.; Medeiros, Guilherme Cardoso; Poehls, L. M. Bolzani; Balen, Tiago R.

doi:10.1007/978-3-030-15663-3_2

Cited by 3 publications

(4 citation statements)

References 31 publications

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“…DFO2 and DFO4, which are low resistance open defects, as well as DFB2 and DFB6, which represent high resistances for bridge defects, represent this situation where the cell robustness is reduced. Note that the defect sizes adopted represent weak defects, which means that may not be detectable by manufacturing tests, even those able to detect dynamic faults, according to the results in [23].…”

Section: Influence Of Resistive Defects On Seu Reliabilitymentioning

confidence: 99%

Evaluation of Single Event Upset Susceptibility of FinFET-based SRAMs with Weak Resistive Defects

et al. 2021

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Fin Field-Effect Transistor (FinFET) technology enables the continuous downscaling of Integrated Circuits (ICs), using the Complementary Metal-Oxide Semiconductor (CMOS) technology in accordance with the More Moore domain. Despite demonstrating improvements on short channel effect and overcoming the growing leakage problem of planar CMOS technology, the continuity of feature size miniaturization tends to increase sensitivity to Single Event Upsets (SEUs) caused by ionizing particles, especially in blocks with higher transistor densities such as Static Random-Access Memories (SRAMs). Variation during the manufacturing process has introduced different types of defects that directly affect the SRAM's reliability, such as weak resistive defects. As some of these defects may cause dynamic faults, which require more than one consecutive operation to sensitize the fault at the logic level, traditional test approaches may fail to detect them, and test escapes may occur. These undetected faults, associated with weak resistive defects, may affect the FinFET-based SRAM reliability during its lifetime. In this context, this paper proposes to investigate the impact of ionizing particles on the reliability of FinFET-based SRAMs in the presence of weak resistive defects. Firstly, a TCAD model of a FinFET-based SRAM cell is proposed allowing the evaluation of the ionizing particle’s impact. Then, SPICE simulations are performed considering the current pulse parameters obtained with TCAD. In this step, weak resistive defects are injected into the FinFET-based SRAM cell. Results show that weak defects can positively or negatively influence the cell reliability against SEUs caused by ionizing particles.

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Section: Influence Of Resistive Defects On Seu Reliabilitymentioning

confidence: 99%

Evaluation of Single Event Upset Susceptibility of FinFET-based SRAMs with Weak Resistive Defects

et al. 2021

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“…In this work, the critical resistance (Rcrit) is the defect resistance threshold that results in a bit-flip when injected the ionizing particle. The methodology for resistive defects injection is the same used in [7] and [18]. Fig.…”

Section: Injecting Resistive Defectsmentioning

confidence: 99%

“…Examples are DFO2 and DFO4, which are low resistance open defects, as well as DFB2 and DFB6, which represent high resistances for bridge defects (weak defects). These values of defects may not be detectable in production tests, even those considering dynamic faults, according to the results in [18].…”

Section: Influence Of Resistive Defects On Seu Reliabilitymentioning

confidence: 99%

Evaluating the Impact of Ionizing Particles on FinFET -based SRAMs with Weak Resistive Defects

Copetti

Medeiros

Taouil

et al. 2020

2020 IEEE Latin-American Test Symposium (LATS)

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Fin Field-Effect Transistor (FinFET) technology enables the continuous downscaling of Integrated Circuits (ICs), using the Complementary Metal-Oxide Semiconductor (CMOS) technology in accordance with the More Moore domain. Despite demonstrating improvements on short channel effect and overcoming the growing leakage problem of planar CMOS technology, the continuity of feature size miniaturization allowed by FinFETs tends to increase sensitivity to Single Event Upsets (SEUs) caused by ionizing particles, especially in blocks with higher transistor densities as Static Random-Access Memories (SRAMs). Variation during the manufacturing process has introduced different types of defects that directly affect the SRAM's reliability, such as weak resistive defects. As some of these defects may cause dynamic faults, which require more than one consecutive operation to sensitize the fault at the logic level, traditional test approaches may fail to detect them and test escapes can occur. These undetected faults associated with weak resistive defects may affect the FinFET-based SRAM reliability during the lifetime. In this context, this paper proposes to investigate the impact of ionizing particles on the reliability of FinFET-based SRAMs in the presence of weak resistive defects. Firstly, a TCAD model of a FinFET-based SRAM cell is proposed in order to allow the evaluation of the ionizing particle's impact. Then, SPICE simulations are performed considering the current pulse parameters obtained with TCAD. In this step, weak resistive defects are injected into the FinFETbased SRAM cell. Results show that weak defects may have either a positive or negative influence on the cell reliability against SEUs caused by ionizing particles.

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“…Works by Van de Goor et al [9], Hamdioui et al [4], and Dillilo et al [10] are examples of such methodology. More recently, researchers have also started to analyze faulty behavior in FinFET SRAMs [11][12][13][14]. This methodology led to many different March algorithms [10,[15][16][17][18].…”

Section: Introductionmentioning

confidence: 99%

Hard-to-Detect Fault Analysis in FinFET SRAMs

Medeiros

Fieback

et al. 2021

IEEE Trans. VLSI Syst.

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Manufacturing defects can cause Hard-to-Detect (HTD) faults in FinFET SRAMs. Detection of these faults, such as random read outputs and out-of-spec parametric deviations, is essential when testing FinFET SRAMs. Undetected HTD faults result in test escapes, which lead to early in-field failures. This paper presents a detailed analysis of HTD faults in FinFET SRAMs by exploring their sensitization and discussing solutions to improve HTD fault coverage during manufacturing testing. We first define the fault space for SRAMs and classify all faults in the space. Following this, we perform a systematic fault analysis based on injecting resistive defects in a memory cell, inspecting its behavior, and identifying HTD faults. Furthermore, we survey existing test solutions and discuss their HTD fault coverage and limitations. Based on our analysis, it is clear that no single test solution can fully detect all HTD faults, thus leading to test escapes. Hence, there is a need for new and more efficient test solutions. Improved detection of HTD faults could be achieved by using parametric test solutions, proposing solutions that cover yet-untargeted HTD faults, combining multiple test approaches into a single solution, and further exploring stress conditions. These new approaches would reduce test escapes and therefore improve the quality of FinFET SRAMs.

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Evaluating the Impact of Resistive Defects on FinFET-Based SRAMs

Cited by 3 publications

References 31 publications

Evaluation of Single Event Upset Susceptibility of FinFET-based SRAMs with Weak Resistive Defects

Evaluation of Single Event Upset Susceptibility of FinFET-based SRAMs with Weak Resistive Defects

Evaluating the Impact of Ionizing Particles on FinFET -based SRAMs with Weak Resistive Defects

Hard-to-Detect Fault Analysis in FinFET SRAMs

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