Evaluating the Performances of the Ultralow Power Magnetoelectric Random Access Memory With a Physics-Based Compact Model of the Antiferromagnet/Ferromagnet Bilayer

Liao, Yu-Ching; Hsu, Chia-Sheng; Nikonov, Dmitri E.; Chang, Sou-Chi; Li, Hai; Young, Ian A.; Naeemi, Azad

doi:10.1109/ted.2022.3159767

Cited by 10 publications

(6 citation statements)

References 22 publications

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“…Fig. 1 shows the schematics and layouts for SOT-, STT-, and ME-MRAM cells based on earlier works [9], [10]. SOTand ME-MRAM cells use two separate transistors for read and write operations while STT-MRAM uses a single transistor for both operations.…”

Section: Mram Device Modelingmentioning

confidence: 99%

Impact of Technology Scaling and Back-End-of-the-Line Technology Solutions on Magnetic Random-Access Memories

Kumar,

Shim,

Narla

et al. 2024

IEEE J. Explor. Solid-State Comput. Devices Circuits

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While magnetic random-access memories (MRAMs) are promising thanks to their non-volatility, relatively fast speeds, and high endurance, there are major challenges in adopting them for the advanced technology nodes. One of the major challenges in scaling MRAM devices is caused by the everincreasing resistances of interconnects. In this paper, we first study the impact of shrunk interconnect dimensions on MRAM performance at various technology nodes. Then, we investigate the impact of various potential back-end-of-the-line (BEOL) technology solutions at the 7nm node. Based on interconnect resistance values from TCAD simulations and MRAM device characteristics from experimentally validated/calibrated physical models, we quantify the potential array-level performance of MRAM using SPICE simulations. We project that some potential BEOL technology solutions can reduce the write energy by up to 34.6% with spin-orbit torque (SOT) MRAM, and 29.0% with spin-transfer torque (STT) MRAM. We also observe up to 21.4% reduction in the read energy of the SOT-MRAM arrays.

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Section: Mram Device Modelingmentioning

confidence: 99%

Impact of Technology Scaling and Back-End-of-the-Line Technology Solutions on Magnetic Random-Access Memories

Kumar,

Shim,

Narla

et al. 2024

IEEE J. Explor. Solid-State Comput. Devices Circuits

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“…Fig. 3 shows the SPICE simulation waveforms for 118 the write operation using compact models for the BFO/CoFe 119 heterostructure [33].…”

Section: A Write Operation 109mentioning

confidence: 99%

“…In this article, we propose a compact ME-magnetic random access memory (MRAM)-based TCAM (ME-TCAM) cell that uses only three transistors and two MTJs and demonstrates its benefits in terms of density and writes and search operations compared to alternative implementations based on SRAM and FeFET. Experimentally validated/calibrated compact models and micromagnetic simulations [31]- [33] are used to evaluate the write operation and to study the tradeoff between the write energy and retention time.…”

mentioning

confidence: 99%

Modeling and Design for Magnetoelectric Ternary Content Addressable Memory (TCAM)

Narla

Kumar

Laguna

et al. 2022

IEEE J. Explor. Solid-State Comput. Devices Circuits

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This article proposes a novel magnetoelectric (ME) effect-based ternary content addressable memory (TCAM). The potential array-level write and search performances of the proposed ME-TCAM are studied using experimentally calibrated compact physical models and SPICE simulations. The voltage-controlled operation of the ME devices eliminates the large joule heating present in the current-controlled magnetic devices and their low-voltage write operation makes them more energy-efficient compared to static random access memory-based TCAMs (SRAM-TCAMs). The proposed compact TCAM outperforms its SRAM counterpart with 1.35× and 14.4× improvements in search and write energy, respectively, and its nonvolatility eliminates the standby leakage. We project an error rate below 10 −4 while considering various sources of variation in magnetic and CMOS devices. At the application level, using memory-augmented neural networks (MANNs), we project a 2× energy-delay-area-product (EDAP) improvement over an SRAM-TCAM. 12 13 14 INDEX TERMS BiFeO 3 (BFO), magnetoelectric (ME), ME-magnetic random access memory (MRAM), memory-augmented neural network (MANN), micromagnetic, multiferroic, ternary content addressable memory (TCAM).I. INTRODUCTION 15 W ITH the ever growing limits imposed by intercon-16 nects, novel computing paradigms that may reduce 17 data traffic between logic and memory have become more 18 attractive. Various in-memory computing approaches [1] 19 are therefore being explored in the context of different 20 applications/domains such as neural networks [2], associative 21 memories [3], spin-torque nano-oscillators [4], probabilistic 22 computing [5], and reservoir computing [6]. Ternary content 23 addressable memory (TCAM) is an associative memory that 24 performs parallel data searches over a memory array and 25 outputs if/where a match occurs. TCAMs have been used 26 in a variety of applications, such as few-shot learning [7], 27 [8], deoxyribonucleic acid (DNA) read alignment [9], 28 deep random forest [10], and hyperdimensional comput-29 131 proper choice of device parameters, this would happen only 132 when there is a mismatch between the stored and search data. 133 If the search bit is ''X,'' then SL and SL are grounded, 134 which prevents T3 from discharging ML. If the stored bit 135 is ''X,'' then both MTJs are in the anti-parallel state and 136 V fix∼V s/2 . We use appropriate threshold voltages to ensure 137 that V s /2 is adequately lower than the threshold voltage of 138 T3 to prevent T3 from discharging ML. Table 2 summarizes 139 the search operation for all possible stored and search bits 140 combinations. It should be noted that kV s < V s /2, where 141 k ≡ R p /(R p + R ap ) (R p and R ap are the resistances of the 142 MTJs in the parallel and anti-parallel state, respectively).143Hence, the worst case in terms of the margins and the leakage 144 current in T3 is when a ''don't care'' bit is stored. V s values 145 and MTJ device parameters are discussed later in Section IV.

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“…4(a,b). The extracted parameters are then used in the compact model 17 developed based on Landau-Khalatnikov (LK) equation for the polarization dynamics and Landau-Lifshitz-Gilbert (LLG) equation for the magnetization dynamics. The magnetization switching time depends on the polarization switching time (t F E ); however, if polarization switches too fast, magnetization may not be able to respond and will result in switching failure (Fig.…”

Section: Me-mrammentioning

confidence: 99%

“…At the modeling front, compact models have been developed for both SOT-MRAM 16 and ME-MRAM. 17 At the circuits and systems level, SOT-MRAM based deep neural network (DNN) inference has been proposed and experimentally demonstrated. 1 An all-spin artificial neural network based on SOT driven domain wall motion has been proposed as well.…”

Section: Introductionmentioning

confidence: 99%

Crosslayer modeling and design for spin-orbit-torque and magnetoelectric memory arrays and compute-in-memory

et al. 2022

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A diverse set of novel materials, physical phenomena, logic/memory devices, and circuit/system options/concepts are being pursued globally to design and develop the next generations of information storage and processing platforms. Many of these potential options are vastly different compared to their conventional counterparts and cannot be used as drop-in replacements. This research should therefore include several levels of abstraction, and must take a holistic approach to truly leverage the benefits offered by the promising options. Among the emerging materials and devices, magnetic and multiferroic devices are of particular interest thanks to their non-volatility, density, energy efficiency and durability. This paper presents a co-design framework for magnetic materials, devices, and memory arrays based on a hierarchy of physical models. Two major categories of devices are considered: spin-orbit-torque (SOT) and magnetoelectric (ME) random access memories. Circuit compatible experimentally validated/calibrated physical models for such devices is presented and used to optimize material and device parameters to minimize energy/delay for read and write operations for various target error rates. Finally, novel SOT and ME based cell designs for ternary content-addressable memories (TCAM) are presented and their potential performance is quantified against their SRAM and FeFET based designs using a comprehensive modeling and benchmarking framework.

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Evaluating the Performances of the Ultralow Power Magnetoelectric Random Access Memory With a Physics-Based Compact Model of the Antiferromagnet/Ferromagnet Bilayer

Cited by 10 publications

References 22 publications

Impact of Technology Scaling and Back-End-of-the-Line Technology Solutions on Magnetic Random-Access Memories

Impact of Technology Scaling and Back-End-of-the-Line Technology Solutions on Magnetic Random-Access Memories

Modeling and Design for Magnetoelectric Ternary Content Addressable Memory (TCAM)

Crosslayer modeling and design for spin-orbit-torque and magnetoelectric memory arrays and compute-in-memory

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