Evaluation of Physical Unclonable Functions for 28-nm Process Field-Programmable Gate Arrays

Abstract

In this study, the properties of physical unclonable functions (PUFs) for 28-nm process field-programmable gate arrays (FPGAs) are examined. A PUF is a circuit that generates device-specific IDs by extracting device variations. Owing to device variation, no two PUFs will generate the same ID even if they have identical structures and are manufactured on the same silicon wafer. However, because the influence of device variation increases as the size of the process node shrinks, it is uncertain whether PUFs can be built using recently developed small-scale process nodes, even though the technology of variation control is constantly advancing. While many PUFs using 40-nm or larger process nodes have been reported, smaller devices have not yet been studied to the authors' knowledge, and this is the first published journal article on PUFs for 28-nm process FPGAs. In this paper, within-die reproducibility, die-to-die uniqueness, and other properties are evaluated, and the feasibility of PUFs on 28-nm FPGAs is discussed.

A Flip-Flop Based Arbiter Physical Unclonable Function (APUF) Design with High Entropy and Uniqueness for FPGA Implementation

“…• A conventional APUF design with a balanced routing is presented and implemented on Xilinx Artix-7 FPGAs. Both the previously proposed FF-APUF [7] and the improved APUF achieve better uniqueness results than the previous work [11] on FPGA. • The two most widely used machine learning based modelling attacks, linear regression (LR) and covariance matrix adaptation evolution strategies (CMA-ES), are utilized to evaluate the resistance of the FF-APUF design.…”

“…Therefore, many previous designs are difficult to implement on FPGA due to the difficulty of implementation of balanced delay lines. Although Majzoobi et al [21] and Hori et al [11] have implemented APUFs on FPGAs, they introduced an additional tuning circuit or reported results with low uniqueness.…”

“…the more complex the underlying PUF architecture, the more difficult the adversary to break a PUF. We utilize Shannon entropy, as given in Eq (11), to assess the complexity of each stage. It allows us to compare the uncertainty introduced by process variations in each stage between the two designs.…”

“…In this section, the FPGA implementations of both the FF-APUF and APUF designs are presented. An implementation of a 64-stage conventional APUF design on the Nexys4 board with a Xilinx Artix-7 FPGA has been proposed in [11]. In this implementation, each of the two delay chains requires 64 slices, with the arbiter (an FF) placed in an additional, separate slice.…”

A lightweight and secure-enhanced Strong PUF design on FPGA

“…These problems limit the application of the arbiter PUF in FPGAs authentication. In general, the stability and response uniqueness of Weak PUF is better than the existing Strong PUF design [20,21]. Realizing Strong PUF with stable and mature Weak PUF becomes a feasible design method.…”