Evaluation of predicated array data-flow analysis for automatic parallelization

Moon, Sungdo; Hall, Mary

doi:10.1145/301104.301112

Cited by 22 publications

(6 citation statements)

References 24 publications

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“…Other sophisticated approaches exist that produce predicates that may be used either at compile-time or at runtime, depending on whether there is enough information available [Moon and Hall 1999;Pugh and Wonnacott 1998]. …”

Section: Runtime Dependence Testsmentioning

confidence: 99%

Dynamic memory interval test vs. interprocedural pointer analysis in multimedia applications

Salamí

Valero

2005

ACM Trans. Archit. Code Optim.

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Techniques to detect aliasing between access patterns of array elements are quite effective for many numeric applications. However, although multimedia codes usually follow very regular memory access patterns, current commercial compilers remain unsuccessful in disambiguating them due mainly to complex pointer references. The Dynamic Memory Interval Test is a runtime memory disambiguation technique that takes advantage of the specific behavior of multimedia memory access patterns. It evaluates whether or not the full loop is disambiguated by analyzing the region domain of each load or store before each invocation of the loop.This paper provides a detailed evaluation of the approach, compares it against an advanced interprocedural pointer analysis framework, and analyzes the possibility of using both techniques at the same time. Both techniques achieve similar speedups separately (1.25X in average for a 8-issue width architecture). Furthermore, they can be used together to improve performance (reaching an average speed-up of 1.32X). Results also confirm that memory disambiguation is a key optimization to exploit the available parallelism in multimedia codes, especially for wide-issue architectures (1.50X average speed-up when scaling from 4-to 12-issue width in contrast to a low 1.10X for the baseline compiler).

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Section: Runtime Dependence Testsmentioning

confidence: 99%

Dynamic memory interval test vs. interprocedural pointer analysis in multimedia applications

Salamí

Valero

2005

ACM Trans. Archit. Code Optim.

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“…In this section, we present an overview of predicated array data-flow analysis. A more complete treatment is found elsewhere [19,20]. This technique can be used to parallelize the 45 loops that fall into the CF, BC and CF+BC categories from the experiment in the previous section.…”

Section: Predicated Array Data-flow Analysismentioning

confidence: 99%

“…While space considerations preclude a formal description of predicated array data-flow analysis, we touch on what modifications to an existing array data-flow analysis are required to realize this solution. The technique is described in more detail elsewhere [19,20].…”

Section: Description Of Techniquementioning

confidence: 99%

Combining Compile‐Time and Run‐Time Parallelization

Moon

Hall

1999

Scientific Programming

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This paper demonstrates that significant improvements to automatic parallelization technology require that existing systems be extended in two ways: (1) they must combine high‐quality compile‐time analysis with low‐cost run‐time testing; and (2) they must take control flow into account during analysis. We support this claim with the results of an experiment that measures the safety of parallelization at run time for loops left unparallelized by the Stanford SUIF compiler’s automatic parallelization system. We present results of measurements on programs from two benchmark suites – SPECFP95and NASsample benchmarks – which identify inherently parallel loops in these programs that are missed by the compiler. We characterize remaining parallelization opportunities, and find that most of the loops require run‐time testing, analysis of control flow, or some combination of the two. We present a new compile‐time analysis technique that can be used to parallelize most of these remaining loops. This technique is designed to not only improve the results of compile‐time parallelization, but also to produce low‐cost, directed run‐time tests that allow the system to defer binding of parallelization until run‐time when safety cannot be proven statically. We call this approachpredicated array data‐flow analysis. We augment array data‐flow analysis, which the compiler uses to identify independent and privatizable arrays, by associating predicates with array data‐flow values. Predicated array data‐flow analysis allows the compiler to derive “optimistic” data‐flow values guarded by predicates; these predicates can be used to derive a run‐time test guaranteeing the safety of parallelization.

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“…Many researchers have considered predication the promising parallelism extraction technique. This encouraged optimization researches to propose modifications for better resources utilization under predication in hyper-blocks [1,2,4,6,7,8,9,11,13,17,18,21].…”

Section: Introductionmentioning

confidence: 99%

Hybrid predication model for instruction level parallelism

Ashmawy

Ismail²,

Fahmy³

2002

Proceedings 16th International Parallel and Distributed Processing Symposium

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This paper presents a hybrid predication model in analogy to the delayed branching technique with overlapped delayed slots by integrating two different predication models. Predicated-execution is considered a promising branch handling technique. A few models have been proposed for predicated-execution, the most known model has succeeded to provide ILP processors with enough parallel instructions for efficient resources utilization. Unfortunately, false parallelism is introduced by the instructions provided from the nullified paths (large dynamic code expansion). Another predicatedexecution model has managed to decrease the dynamic code expansion, with the cost of limiting the parallelism exploited and increasing the static code expansion. The presented hybrid predication model managed to integrate the advantages of the two models by decreasing the code expansion both dynamically and statically, especially for conditional code structures included within loops. The various conducted experiments aimed to provide an evaluation for the proposed model via simulator. The results proved that the presented hybrid predication model can achieve better utilization of register and shorter schedules with the same issue-width compared with the other existing models.

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Evaluation of predicated array data-flow analysis for automatic parallelization

Cited by 22 publications

References 24 publications

Dynamic memory interval test vs. interprocedural pointer analysis in multimedia applications

Dynamic memory interval test vs. interprocedural pointer analysis in multimedia applications

Combining Compile‐Time and Run‐Time Parallelization

Hybrid predication model for instruction level parallelism

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