2016
DOI: 10.1007/s10470-016-0763-8
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Evaluation of size influence on performance figures of a single photon avalanche diode fabricated in a 180 nm standard CMOS technology

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Cited by 6 publications
(8 citation statements)
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“…Work in [33] reports similar DCR to the DCR value of our SPAD with a reduced PDP peak value. Our SPAD compared to the other works in the 180 nm node [35], [42] shows a higher PDP peak at a lower DCR value.…”
Section: B Photon Detection Probabilitysupporting
confidence: 74%
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“…Work in [33] reports similar DCR to the DCR value of our SPAD with a reduced PDP peak value. Our SPAD compared to the other works in the 180 nm node [35], [42] shows a higher PDP peak at a lower DCR value.…”
Section: B Photon Detection Probabilitysupporting
confidence: 74%
“…It can be noted that the 480 nm peak reduces to 55% when the DUT was operated at 4 V and to 48% at 3 V whilst it drastically reduces to 32% at 2 V. The reported curve is the average of two measurements and the error bars show the range of measurement. PDP is a function of doping levels, noise, excess bias and active area [33], therefore the obtained PDP is achieved thanks to the low noise of device, compared to other 180 nm HV SPADs which will have comparable doping levels, and a larger active area in lieu of the square shape. Fig.…”
Section: B Photon Detection Probabilitymentioning
confidence: 97%
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“…1(a), a typical shallow P+/N-well junction structure is used to illustrate the modeling method of timing jitter. This SPAD device mainly consists of a P+ implantation layer and an N-well that form a shallow depletion region and two neutral regions [15]. Under the excess bias state, once the photons are incident onto these three regions, the photonic carriers will be produced and spread over the entire detection area, as shown in Fig.…”
Section: Physical Mechanism Of Photon Detectionmentioning
confidence: 99%
“…To validate the proposed model, the analytical results are compared with the reported measured data [20]. Although the compared SPAD device is fabricated in a different 0.18 µm standard CMOS technology [15], [20], it has the same P+/N-well structure (see Fig. 1(a)) and the same active diameter with our modeling device.…”
Section: Excessive Voltagementioning
confidence: 99%