Evaluation of the I_max-f_sw-dv/dt Trade-off of High Voltage SiC MOSFETs Based on an Analytical Switching Loss Model

Abstract

Advanced high voltage (3.3-15kV) SiC MOSFETs have been developed for future medium voltage converters over the past decade due to their superior performance. In order to better understand the operation limits and potential of these devices, this paper evaluates the I max -f sw -dv/dt trade-off (maximal currenthandling capability at a specific switching frequency and at a defined switching speed) for high voltage SiC MOSFETs based on a proposed linearized analytical switching loss model. There, high voltage SiC MOSFETs manufactured by Cree combined with data from literature for scaling are used as reference.

Analytical Calculation of the Residual ZVS Losses of TCM-Operated Single-Phase PFC Rectifiers

“…In ZVS implementations, however -like the TCM topology here -the measured "switching" losses are higher-than-expected and increase with current, necessitating the inclusion of an additional switching loss mechanism beyond C oss losses. While comprehensive analytical models of switching behavior have been previously given (for example, [30,31]), we focus on a minimum-complexity equivalent circuit (and resulting equations) to ascertain the core driver of these residual ZVS losses. Fig.…”

An Analytical Switching Loss Model for a SiC MOSFET and Schottky Diode Half-Bridge Based on Nonlinear Differential Equations

“…Fig. 1 depicts the considered equivalent circuit for a hard-switched SiC MOSFET and a SiC Schottky diode half-bridge [11], where all relevant parasitics from the device packages and the PCB layout are included. The model assumptions/simplifications are: A1) A lumped parasitic inductance L PCB resulting from the PCB traces in the power loop is assumed.…”

“…Fig. 4 depicts the exemplary switching waveforms of the C3M0075120D and C4D10120H half-bridge including turn-on, hard turn-off, and ZVS turn-off transitions [11], obtained by solving this NDAE set including the parasitics listed in Table II Fig. 4: Switching waveforms for a turn-on transition at V in =800 V, I L =20 A in (a), for a hard turn-off transition at V in =800 V, I L =20 A in (b), and for a ZVS turn-off transition at V in =800 V, I L =5 A in (c).…”

“…In the following, the turn-on transition is briefly analyzed based on the step-by-step switching interval analysis in [11]. To solve the system equation set in (10), both the initial and the end states of each interval are required.…”

Load-Independent Voltage Balancing of Multi-Level Flying Capacitor Converters in Quasi-2-Level Operation

“…The bridgeleg's output voltage thus transitions between the two DC voltage levels (positive and negative) in a staggered fashion [22][23][24][28][29][30][31][32][33][34]. Note that these staggered transitions of the the Q2L-MMC and Q2L-FCC topologies feature lower average dv/dt compared to the (MV) 2-level converters, which is beneficial for the design of EMI filters and magnetics such as medium-frequency transformers, and lowers the stress of the electric insulation [29,[35][36][37][38].…”