Evaluation of the temperature influence on SEU vulnerability of DICE and 6T-SRAM cells

Abstract

In this paper, we evaluate the temperature influence on the vulnerability to single event upsets (SEU) of 6transistor static random access memory (6T-SRAM) cells and dual interlocked storage cells (DICE). The critical charge (Qcrit, minimum charge capable of generating an SEU) is evaluated for 65nm, 45nm, 32nm and 22nm bulk CMOS technologies and temperatures between -50°C and 150°C. A double exponential signal is used to model the current pulse generated by ionizing particles. SPICE simulations have shown that Qcrit is sensibly reduced by the rise of temperature. Qcrit variations of up to 88.4% and 99.9% have been calculated for 6T-SRAM and DICE cells, respectively.

Effect of temperature on heavy ion-induced single event transient on 16-nm FinFET inverter chains

“…For example, Farjallah et al evaluated the variation of Q crit with temperature for 65-nm, 45-nm, 32-nm, and 22-nm bulk silicon CMOS technologies in a temperature range from −50 • C to 150 • C. The SPICE simulation results indicated that Q crit decreases significantly as temperature increases for 6T-SRAM and DICE units, the calculated Q crit changes 88.4% and 99.9% respectively. [21] In 2016, Zhang et al characterized the soft error rate (SER) triggered by α particles in 20-nm bulk silicon planar device and 16-nm bulk silicon FinFET technology at different temperatures and power supply voltages. The test results showed that in the same temperature range, the SER of 16-nm FinFET did not change significantly with temperature, while the SER of the 20-nm planar device increases about twice at elevated temperature.…”