Evaluation, optimization, and reliability of no-flow underfill process

Colella, M.; Baldwin, D.

doi:10.1109/isapm.2002.990389

Cited by 4 publications

(2 citation statements)

References 17 publications

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“…1(a). The applied no-flow assembly technique used the line edge dispense pattern to prevent a chip's placement from inducing voids [12], [22], [23]. Then, the assembled packages were reflowed according to a full factorial design of experiment (DOE) described in Tables IV(a) and IV(b), respectively.…”

Section: A Assembly Yield Characterizationmentioning

confidence: 99%

Near Void-Free Assembly Development of Flip Chip Using No-Flow Underfill

Yim

Master

et al. 2009

IEEE Trans. Electron. Packag. Manufact.

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The advanced flip-chip-in-package (FCIP) process technology, using no-flow underfill material for high I/O density (over 3000 I/O) and fine-pitch (down to 150 m) interconnect applications, presents challenges for flip chip processing because underfill void formation during reflow drives interconnect yield down and degrades reliability. In spite of such challenges, a high yield, reliable assembly process ( 99 99%) has been achieved using commercial no-flow underfill material with a high I/O, fine-pitch FCIP. This has been obtained using design of experiments with physical interpretation techniques. Statistical analysis determined what assembly conditions should be used in order to achieve robust interconnects without disrupting the FCIP interconnect structure. However, the resulting high yield process had the side effect of causing a large number of voids in the FCIP assemblies. Parametric studies were conducted to develop assembly process conditions that would minimize the number of voids in the FCIP induced by thermal effects. This work has resulted in a significant reduction in the number of underfill voids. This paper presents systematic studies into yield characterization, void formation characterization, and void reduction through the use of structured experimentation which was designed to improve assembly yield and to minimize the number of voids, respectively, in FCIP assemblies.

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Section: A Assembly Yield Characterizationmentioning

confidence: 99%

Near Void-Free Assembly Development of Flip Chip Using No-Flow Underfill

Yim

Master

et al. 2009

IEEE Trans. Electron. Packag. Manufact.

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“…Further process development should focus on the L and U patterns because they are the most practical in terms of conserving board space. Additional modeling work has been completed to determine the underfill wet-out distance as a function of time for different dispense patterns and underfill viscosities [12]. A near void free no flow underfill dispense process was developed including a novel ranking methodology for improved reflow process characterization.…”

Section: Discussionmentioning

confidence: 99%

Void free processing of flip chip on board assemblies using no-flow underfills

Colella

Baldwin

2004 1st IEEE Consumer Communications and Networking Conference (IEEE Cat. No.04EX745)

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A consistent problem that has plagued the introduction of innovative no-flow underfill materials into volume flip chip onboard/in-package production is voiding of the underfill during processing. In addition to outgassing voids typically due to moisture and solvents in the substrate or outgassing of the underfill, voids are produced as a result of the squeeze flow experience by the underfill during chip placement. This paper presents a systematic development of optimal flip chip on board assembly process for no flow underfill materials presenting process parameters compatible with four commercially available no flow fluxing underfills. A novel hybrid process is developed that combines a capillary flow dynamic with no-flow fluxing underfills resulting in virtually a void free assembly process.Experiments are conducted to investigate the dispense pattern, placement speed and the impact of the placement process on interconnect yield further investigating the dispense pattern, placement force, and dwell time. A dispensed line pattern location and chip placement study is conducted to determine how voiding is affected by the position of the dispensed line in relation to the side of the die. The results of these experimental studies are used to select an optimal placement process for the materials. Reflow profile parameters are investigated using a parametric approach. The results of these initial studies are used to choose an optimal process for the materials. Test boards are assembled according to the optimal process for each material, and air to air thermal cycle, AATC, thermal cycling test is performed to qualify the assemblies. The newly developed edge patterned hybrid no-flow process has resulted in near void-free assemblies capable of passing 2000 cycles without an electrical failure for the -40 to 125 °C AATC reliability test.

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Near void free hybrid no-flow underfill flip chip process technology

Colella

Baldwin

2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546)

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Evaluation, optimization, and reliability of no-flow underfill process

Cited by 4 publications

References 17 publications

Near Void-Free Assembly Development of Flip Chip Using No-Flow Underfill

Near Void-Free Assembly Development of Flip Chip Using No-Flow Underfill

Void free processing of flip chip on board assemblies using no-flow underfills

Near void free hybrid no-flow underfill flip chip process technology

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