Event Driven Modeling and Characterization of the Second Order Voltage Switched Charge Pump PLL

Abstract

International audienceThe charge pump phase locked loop (CP-PLL) is widely used subsystem in modern mixed-signal electronic systems that are utilized in digital and wireless applications such as clock generation, synchronization and frequency synthesis. In the classical mode, the combination of a current switched charge pump and a digital phase and frequency detector (CP-PFD) circuits produces an ideal pulse width modulated constant current during one sampling period, which permits a suitable transient performance. Nevertheless, many commercially used CP-PLL chips (e.g., 4046 family) have a voltage switched charge pump (VSCP) because the design of the constant voltage source is easier than the constant current generator and it is a low cost solution. However, the VSCP delivers a non-constant pump current, which varies during one sampling period related to the electrical load of the loop filter (LF). This effect results in a varying gain of the control system affecting significantly its tracking ability. Furthermore, due to its hybrid structure, the simulation of the CP-PLL at high frequencies is challenging and the analysis of its transient characteristics during its non-linear acquisition procedure is not easy. In this paper, a first ever exact and nonlinear model based on the phase equations of the second order voltage switched charge pump phase locked loop (VSCP-PLL) is established by using an event driven (ED) technique. This exact model is then simplified by using a step-wise quasi-constant current approximation during one sampling period to obtain the analytical phase equations. The derived ED-model is validated at transistor level simulations using 130 nm CMOS process. Furthermore, some typical nonlinear features of the VSCP-PLL are explored and the developed ED-models are compared with the quasi-time-continuous (QTC) theory

All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops

“…Thus, in order to fully understand the effects of structural faults on output signal of CP-PLL, the structure, operation and sensitivity of CP-PLL will be first studied. Figure 1 shows a classical structure of CP-PLL [23,24]. It consists of five functional blocks, including phase/frequency detector (PFD), charge-pump (CP), loop filter (LF), VCO and divide-by-N frequency divider (DBN).…”

Simulations of 3^rd order voltage switched CP-PLL using a fast event switching macromodeling

“…This voltage switch outputs in three states [V DD , ctrl , V SS ] and it produces a non-constant pump current due to electrical load of the LF (as shown in Fig. 2) [3]- [6].…”

“…Since the PFD is triggered by the falling or rising edges of the non-uniformly sampled signals therefore, EDapproach is natural to apply on the CP-PLL system [6]- [10]. The principle of the event switching methodology is explained based on VSCP topology is shown in Fig.4.…”

“…However discrete-time (DT) non-linear methods are more efficient and growing methodology for characterizing the timing based switching state of the CP-PLL [6]- [14]. The DT event-driven (ED) approach provides an ultra-fast (few seconds simulation time) simulation, exact system level and iterative representation of the system by allowing its modular concept [6]- [12]. Moreover, it features the off-locking behavior of the system with exact differential relations.…”

An improved phase digitization mechanism for fast-locking low-power all-digital PLLs

“…All-digital phaselocked loops (ADPLLs) [1,2,3,4,5,6] are preferred in nanoscale CMOS with the merits of lower cost, power consumption, area and shorter locking time comparing to analog PLLs [7,8]. In a counter-assisted ADPLL [1,2,3,4,5], time-to-digital converter (TDC) is employed as fractional phase detector and measures edge time difference between the high-frequency output clock CKV and reference clock FREF.…”