Evolution of Graphics Northbridge Test and Debug Architectures Across Four Generations of AMD ASICs

Margulis, A.; Akselrod, D.; Rentschler, Eric; Ricchetti, Mike

doi:10.1109/mdat.2013.2274651

Cited by 4 publications

(4 citation statements)

References 11 publications

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“…For example, during yield learning, an embedded memory might be tested several times by running multiple BIST algorithms. Another example is reading out the memory contents for diagnostic purposes [11]. In both examples many accesses might be needed.…”

Section: B Study Of Robustnessmentioning

confidence: 99%

Design, Verification, and Application of IEEE 1687

Zadegan

Larsson

Jutman³

et al. 2014

2014 IEEE 23rd Asian Test Symposium

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Abstract-IEEE 1687 (IJTAG) has been developed to enable flexible and automated access to the increasing number of embedded instruments in today's integrated circuits. These instruments enable efficient post-silicon validation, debugging, wafer sort, package test, burn-in, bring-up and manufacturing test of printed circuit board assemblies, power-on self-test, and in-field test. Current paper presents an overview of challenges as well as selected examples in the following topics around IEEE 1687 networks: (1) design to efficiently access the embedded instruments, (2) verification to ensure correctness, and (3) fault management at functions performed in-field through the product's life time.

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Section: B Study Of Robustnessmentioning

confidence: 99%

Design, Verification, and Application of IEEE 1687

Zadegan

Larsson

Jutman³

et al. 2014

2014 IEEE 23rd Asian Test Symposium

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“…For each of these cases-referred to as usage scenarios hereafterit is of interest to access some but not all of the instruments [1]. As an example, a memory built-in-self-test (MBIST) instrument might be accessed (1) during yield learning for a new process to choose the most suitable algorithms, (2) during wafer sort and package test to detect defective devices and perform repair, (3) in the burn-in process to cause activity in the chip and to detect infant mortality [2], [3], (4) during PCB bringup [4], (5) during PCB assembly manufacturing test [4], and (6) during power-on self-test and operator-driven in-field tests. Also, the number of accesses to a given instrument typically varies between different scenarios.…”

Section: Introductionmentioning

confidence: 99%

“…For example, during yield learning, an embedded memory might be tested several times by running multiple BIST algorithms. Another example is reading out the memory contents for diagnostic purposes [5]. In both examples many accesses might be needed.…”

Section: Introductionmentioning

confidence: 99%

Robustness of TAP-based scan networks

Zadegan

Carlsson

Larsson

2014

2014 International Test Conference

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Abstract-It is common to embed instruments when developing integrated circuits (ICs). These instruments are accessed at postsilicon validation, debugging, wafer sort, package test, burn-in, printed circuit board bring-up, printed circuit board assembly manufacturing test, power-on self-test, and operator-driven infield test. At any of these scenarios, it is of interest to access some but not all of the instruments. IEEE 1149.1-2013 and IEEE 1687 propose Test Access Port based (TAP-based) mechanisms to design flexible scan networks such that any combination of instruments can be accessed from outside of the IC. Previous works optimize TAP-based scan networks for one scenario with a known number of accesses. However, at design time, it is difficult to foresee all needed scenarios and the exact number of accesses to instruments. Moreover, the number of accesses might change due to late design changes, addition/exclusion of tests, and changes of constraints. In this paper, we analyze and compare seven IEEE 1687 compatible network design approaches in terms of instrument access time, hardware overhead, and robustness. Given the similarities between IEEE 1149.1-2013 and IEEE 1687, the conclusions are also applicable to IEEE 1149.1-2013 networks.

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“…Accuracy is very important in IC design and manufacturing. In order to adapt to the needs of the development of technology, the design team manage to shorten design period, and make sure the successful tape-out, which depends on the design test in the design [1] .…”

Section: Introductionmentioning

confidence: 99%