Resistive random access memory (RRAM) has emerged as a promising candidate for next-generation nonvolatile memory (NVM) due to its low-voltage operation, fast switching speed and high-density integration [1]. Two common resistive switching (RS) modes in RRAM are unipolar and bipolar modes [2]. A unipolar RRAM in series with a rectifying diode, so-called one diode-one resistor (1D1R) cell, is particularly attractive for high-density applications because of the minimal 4F 2 cell size [3]. However, high RESET current (I RESET ) impedes the cell size scaling in 1D1R array. Recently, we have demonstrated a reliable Ni/HfO 2 /Si unipolar RRAM, fully compatible with the Si technology [4,5]. In this paper, we show that unipolar HfO 2 RRAM exhibits excellent NVM characteristics promising for low-I RESET , low-power operation in the future high-density 1D1R array. In addition, we show that the RS mode can be tailored by a bottom interfacial layer of Al 2 O 3 between HfO 2 and Si. New evidence on the location of filament connections/ruptures and RS mechanism will be discussed in details.After standard RCA clean and a rapid thermal oxidation at 500 °C for 10 s in ambient O 2 on p + -Si substrates, 10-nm HfO 2 , 10-nm HfO 2 /3-nm Al 2 O 3 , and 3-nm Al 2 O 3 were deposited as the RS layers. HfO 2 films were deposited by metal organic chemical vapor deposition at 500 °C using Hf(OtBu) 2 (mmp) 2 and O 2 as precursors, while Al 2 O 3 film was deposited using Al[OCH(CH 3 ) 2 ] 3 and O 2 as precursors. Ni top electrodes with a thickness of 100 nm and a diameter of 200 μm were defined by a shadow mask process. The devices were measured using an Agilent 4156B semiconductor parameter analyzer by applying voltage on the top electrodes while the p + -silicon substrates (bottom electrodes) were grounded.The TEM image in Fig. 1 displays that as-deposited 10-nm HfO 2 was partially crystallized with an interfacial layer between Si and HfO 2 . The Ni/HfO 2 /Si device exhibits nonpolar RS behavior in Fig. 2, where unipolar and bipolar RS by any polarities of SET and RESET voltage were present. The compliance current at SET determined the SET power, the filament morphology, and thus the I RESET [5], as shown in Fig. 3. I RESET was scaled linearly with the compliance current from 1 mA to 100 μA, but saturated between 100 μA and 10 μA because of the charge dissipation current from parasitic capacitors [6]. With a low compliance current of 10 μA at SET, unipolar RS with 80 μA I RESET is depicted in Fig. 4. Figure 5 and Fig. 6 display the statistical distribution of switching voltages and resistance at high/low resistance states under lowpower operation. Very reproducible unipolar RS with stable I RESET below 100 μA, non-overlapped SET/RESET voltage window, and a reasonable resistance ratio of ~ 100 was promising for future high-density 1D1R memory array. Data retention characteristics are presented in Fig. 7. Both high/low resistance states were stable at 85 ℃ for at least 12000s, even when the filament size scaled with I RESET to nanoscale [5]...