Evolution of roughness during the pattern transfer of high-chi, 10nm half-pitch, silicon-containing block copolymer structures

Blachut, Gregory; Sirard, Stephen M.; Liang, Andrew; Mack, Chris A.; Maher, Michael J.; Rincon-Delgadillo, Paulina; Chan, Boon Teik; Mannaert, G.; Vandenberghe, Geert; Willson, C. Grant; Ellison, Christopher J.; Hymes, Diane

doi:10.1117/12.2297489

Cited by 4 publications

(3 citation statements)

References 22 publications

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“…Furthermore, although roughness could add to measurement noise, instrument noise (not due to roughness) can also be mistaken for feature roughness, requiring unbiased analysis techniques. Recent work aims to identify evaluation methods based on roughness origin and impact 23,24,40 , and instrumentation and procedures 19,24,41 .…”

Section: Metrology Challenges For Complex Ic Device Structuresmentioning

confidence: 99%

Metrology for the next generation of semiconductor devices

Badaroglu²,

et al. 2018

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The semiconductor industry continues to produce ever smaller devices that are ever more complex in shape and contain ever more types of materials. The ultimate sizes and functionality of these new devices will be affected by fundamental and engineering limits such as heat dissipation, carrier mobility and fault tolerance thresholds. At present, it is unclear which are the best measurement methods needed to evaluate the nanometre-scale features of such devices and how the fundamental limits will affect the required metrology. Here, we review state-of-the-art dimensional metrology methods for integrated circuits, considering the advantages, limitations and potential improvements of the various approaches. We describe how integrated circuit device design and industry requirements will affect lithography options and consequently metrology requirements. We also discuss potentially powerful emerging technologies and highlight measurement problems that at present have no obvious solution.

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Section: Metrology Challenges For Complex Ic Device Structuresmentioning

confidence: 99%

Metrology for the next generation of semiconductor devices

Badaroglu²,

et al. 2018

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“…X-ray measurements have demonstrated that interfacial roughness varies both between lamellae on the guiding stripe and lamellae on the neutral brush, and as a function of distance from the surface and the substrate . Variations in the LER between lines on different portions of the guiding template have been experimentally observed …”

Section: Introductionmentioning

confidence: 98%

“…11 Variations in the LER between lines on different portions of the guiding template have been experimentally observed. 58 The impact of additives on the BCP structure and thermodynamics has been well established. For systems where the additive is chemically identical to one of the components in the system, the distribution will depend on the ratio of the molecular mass between the additive and its identical component in the BCP.…”

Section: ■ Introductionmentioning

confidence: 99%

Influence of Additives on the Interfacial Width and Line Edge Roughness in Block Copolymer Lithography

et al. 2020

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The challenges of patterning next generation integrated circuits have driven the semiconductor industry to look outside of traditional lithographic methods in order to continue cost effective size scaling. The directed self-assembly (DSA) of block copolymers (BCPs) is a nanofabrication technique used to reduce the periodicity of patterns prepared with traditional optical methods. BCPs with large interaction parameters (χ eff ), provide access to smaller pitches and reduced interface widths. Larger χ eff is also expected to be correlated with reduced line edge roughness (LER), a critical performance parameter in integrated circuits. One approach to increasing χ eff is blending the BCP with a phase selective additive, such as an Ionic liquid (IL). The IL does not impact the etching rates of either phase, and this enables a direct interrogation of whether the change in interface width driven by higher χ eff translates into lower LER. The effect of the IL on the layer thickness and interface width of a BCP are examined, along with the corresponding changes in LER in a DSA patterned sample. The results demonstrate that increased χ eff through additive blending will not necessarily translate to a lower LER, clarifying an important design criterion for future material systems.

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Selective plasma etching of silicon-containing high chi block copolymer for directed self-assembly (DSA) application

Cacho

Benotmane

Pimenta-Barros

et al. 2021

Journal of Vacuum Science &Amp; Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phen

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Directed self-assembly (DSA) of block copolymers (BCPs) is an advanced patterning technique being investigated to obtain small and dense patterns for future technological nodes. In order to demonstrate the potential of DSA to extend optical lithography, poly(styrene-b-methyl methacrylate) (PS-b-PMMA) has been the most commonly used block copolymer in different applications, such as line/space and contact hole patterning as well as uniformity repair. However, the minimum pitch for the PS-b-PMMA system is limited to around 24 nm due to its relatively weak segregation strength. Therefore, block copolymers with stronger microphase segregation have been developed to enable sub-10 nm patterning, thus obtaining the so-called “high chi” BCPs. In this article, the silicon-containing high chi system investigated is the poly(styrene-b-1,1-dimethylsilacyclobutane) (PS-b-PDMSB) presenting a pitch of 18 nm. A one-step top coat and PS removal based on H2/N2 plasma that presents good selectivity and profile has been studied. The H2/N2 gas ratio has been investigated to understand the trade-off between obtaining high selectivity and avoiding pattern collapse. Using this approach, the pattern transfer into different underlayers is demonstrated for the high chi PS-b-PDMSB.

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Evolution of roughness during the pattern transfer of high-chi, 10nm half-pitch, silicon-containing block copolymer structures

Cited by 4 publications

References 22 publications

Metrology for the next generation of semiconductor devices

Metrology for the next generation of semiconductor devices

Influence of Additives on the Interfacial Width and Line Edge Roughness in Block Copolymer Lithography

Selective plasma etching of silicon-containing high chi block copolymer for directed self-assembly (DSA) application

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