Exact lower bound for the number of switches in series to implement a combinational logic cell

Abstract

This paper addresses the question of how many serial switches are necessary to implement a given logic function as a switch network. This issue is important because it affects directly the resistance that will be charging/discharging output loads, thus affecting cell and circuit performance. We derive exact lower bounds to easily evaluate the number of serial switches needed and demonstrate that Complementary Series/Parallel (CSP) and Pass Transistor Logic (PTL) topologies exceed the lower bounds for many practical examples. We also propose a design methodology that will produce cells with minimum number of transistors in series and evaluate the benefits obtained in circuit delay.

CRDOM : Cell Re-Ordering Based Domino On-The-Fly Mapping

“…The higher the dimension of the Domino cell, the wider range of functions it can accommodate. Often, due to reasons like factoring, elimination, substitution the number of logic terms to be realized change drastically [27], [28], though the equivalent function to be realized remains the same. These transformations have an effect on the dimensions of the node.…”

DAG based library-free technology mapping

“…Notice that the number of series transistors in the pull-up is reduced in Fig.1.b, leading to a faster implementation. More details can be found in [15].…”

“…The contribution of this paper is to combine the method for Boolean computation of the number of series transistors presented in [15] with a state of the art technology mapping algorithm inspired by the approach presented in [4]. Significant gains are obtained in delay due to both aspects combined into the proposed mapping tool.…”

“…A recent approach presented in [11] suggests that the addition of some custom cells to a library can improve the speed of the final circuit. Recently, some methods for generating efficient cell networks were proposed [12][13][14][15], including a method [15] to compute the minimum number of transistors in series needed to implement an arbitrary Boolean function. These improvements were presented only at the cell level, lacking of an efficient method for mapping a larger circuit.…”

“…It computes the lower bounds [15] for the number of series transistors in the longest pull-up and pull-down chains of a cell implementing a given logic function. Boolean methods are able to overcome the structural bias [18] of the circuit being mapped, because they do not depend on the DAG structure, but only on the function being mapped.…”