This paper addresses the question of how many serial switches are necessary to implement a given logic function as a switch network. This issue is important because it affects directly the resistance that will be charging/discharging output loads, thus affecting cell and circuit performance. We derive exact lower bounds to easily evaluate the number of serial switches needed and demonstrate that Complementary Series/Parallel (CSP) and Pass Transistor Logic (PTL) topologies exceed the lower bounds for many practical examples. We also propose a design methodology that will produce cells with minimum number of transistors in series and evaluate the benefits obtained in circuit delay.

This paper presents a unified theory to build transistor networks through Binary Decision Diagrams -BDDs. It is able to obtain transistor networks with transistor count near to the best case of other methods presented in the literature. As a result, a pass transistor network implementation is automatically generated for XOR-like gates, since static CMOS performs badly. Similarly, a static CMOS topology is preferred for the generation of NAND-like gates, on which Pass Transistor Logic is not optimal. Variations on the derivation of transistor networks from BDDs are extensively discussed.

This paper presents a comprehensive investigation of how transistor level optimizations can be used to increase design quality of CMOS logic gate networks. Different properties of transistor networks are used to explain features and limitations of different methods. We describe which figures of merit, including the logical effort, affect the design quality of cell transistor networks. Further, we compare six different approaches that generate transistor networks, including two with guaranteed theoretical minimum length transistor chains. This comparison shows that minimum length chains reduce the logical effort of the networks.

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