Unified theory to build cell-level transistor networks from BDDs [logic synthesis]

Abstract

This paper presents a unified theory to build transistor networks through Binary Decision Diagrams -BDDs. It is able to obtain transistor networks with transistor count near to the best case of other methods presented in the literature. As a result, a pass transistor network implementation is automatically generated for XOR-like gates, since static CMOS performs badly. Similarly, a static CMOS topology is preferred for the generation of NAND-like gates, on which Pass Transistor Logic is not optimal. Variations on the derivation of transistor networks from BDDs are extensively discussed.

Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering

“…Table 1 summarizes the properties of the networks under investigation. First column describes the name of the logic, second column lists the transistor types associated to BDD arcs, third column shows if drain inputs are allowed, fourth column details if disjoint planes are used (separated pull-up and pulldown), while the rightmost column shows the use of unateness reduction [22,23]. The derivation of the networks is straightforward from the BDDs.…”

“…1. As the detailed derivation was already presented by other authors, the reader is pointed to references [22,23] for further details. The methods for transistor network generation presented in [7,8,9] are potentially better than the ones derived from BDDs [22,23].…”

“…As the detailed derivation was already presented by other authors, the reader is pointed to references [22,23] for further details. The methods for transistor network generation presented in [7,8,9] are potentially better than the ones derived from BDDs [22,23]. This is a consequence of the fact that BDDs assume bidirectional switches, which is not a restriction to the approach in [7,8,9].…”

BDD decomposition for delay oriented pass transistor logic synthesis

“…Unlike [13], they allow the threshold size of the decomposed BDD's to be varied, and their cost function allows area and depth to be traded off. Poli et al propose techniques for transistor level construction of static CMOS and PTL cells from BDD's and provide a comparison of these logic styles by restricting the number of inputs to a cell to four [18]. Cho and Chen propose a genetic algorithm for technology mapping of mixed static CMOS and PTL circuits using a predefined set of PTL cells [19]; their approach does not specifically target performance driven PTL synthesis.…”

DAG based library-free technology mapping

“…A recent approach presented in [11] suggests that the addition of some custom cells to a library can improve the speed of the final circuit. Recently, some methods for generating efficient cell networks were proposed [12][13][14][15], including a method [15] to compute the minimum number of transistors in series needed to implement an arbitrary Boolean function. These improvements were presented only at the cell level, lacking of an efficient method for mapping a larger circuit.…”