Examination of hot-carrier stress induced degradation on fin field-effect transistor

Abstract

Articles you may be interested inPhysical understanding of different drain-induced-barrier-lowering variations in high-k/metal gate n-channel metal-oxide-semiconductor-field-effect-transistors induced by charge trapping under normal and reverse channel hot carrier stresses Abnormal threshold voltage shift under hot carrier stress in Ti1−xNx/HfO2 p-channel metal-oxide-semiconductor field-effect transistors Hot carrier effect on gate-induced drain leakage current in high-k/metal gate n-channel metal-oxidesemiconductor field-effect transistors Appl. Phys. Lett. 99, 012106 (2011); 10.1063/1.3608241Convergence of hot-carrier-induced saturation-region drain current and linear-region drain current degradation in advanced n-channel metal-oxide-semiconductor field-effect transistors

Abnormal Transconductance Enhancement under Positive Bias Stress in Nanoscale n-Channel Fin Field-Effect-Transistors

“…1c shows the power law with a time exponent 0.14 and 0.15 for long and short channel devices. This conforms to previous literature on PBS in n-MOSFETs, [11][12][13][14] which reported a much lower time power-law exponent, between 0.1 and 0.2, where the carrier trapping from the inversion layer into the oxide bulk defects is the main degradation mechanism. 15 Since PBS is caused by charge trapping in bulk HfO 2 rather than interfacial degradation, S.S. shows no significant change after stress.…”

Study on Intrinsic Hot Carrier Degradation of FinFETs with Different Stress Conditions and Fin Numbers by Decoupling PBTI Component

“…Impact-ionization is well known to introduce interface state generation, which will result in G m and SS degradation. 13 The most severe degradation of G m and SS happens at the largest stress V D , which suggests that the strongest impact-ionization occurs at this stress voltage.…”

Impact of Active Surface Area on Performance and Reliability of Tri-gate FinFET

“…FinFETs are considered a promising candidate for device scaling that surpasses the framework of traditional planar transistors and has a better gate controlling capability, repressing short-channel effects (SCEs) and hot carrier effects (HCEs), and improving the subthreshold swing (SS). (1)(2)(3)(4)(5) Even though fin-based structures may be superior electrically, they are less robust than planar structures mechanically, which may give rise to some unexpected failure mechanisms. (6) Prior studies indicate that mechanical stress shows a great impact on the electrical behavior.…”