Execution modeling in self-aware FPGA-based architectures for efficient resource management

Abstract

Abstract-SRAM-basedFPGAs have significantly improved their performance and size with the use of newer and ultradeep-submicron technologies, even though power consumption, together with a time-consuming initial configuration process, are still major concerns when targeting energy-efficient solutions. System self-awareness enables the use of strategies to enhance system performance and power optimization taking into account run-time metrics. This is of particular importance when dealing with reconfigurable systems that may make use of such information for efficient resource management, such as in the case of the ARTICo 3 architecture, which fosters dynamic execution of kernels formed by multiple blocks of threads allocated in a variable number of hardware accelerators, combined with module redundancy for fault tolerance and other dependability enhancements, e.g. side-channel-attack protection.In this paper, a model for efficient dynamic resource management focused on both power consumption and execution times in the ARTICo 3 architecture is proposed. The approach enables the characterization of kernel execution by using the model, providing additional decision criteria based on energy efficiency, so that resource allocation and scheduling policies may adapt to changing conditions. Two different platforms have been used to validate the proposal and show the generalization of the model: a high-performance wireless sensor node based on a Spartan-6 and a standard off-the-shelf development board based on a Kintex-7.Index Terms-Self-awareness, dynamic and partial reconfiguration, dynamic resource management, FPGAs.

Design of OpenCL-compatible multithreaded hardware accelerators with dynamic support for embedded FPGAs

“…8, where a fixed amount of 2.5 MB of raw data is ciphered by a changing number of hardware accelerators (either containing 1 or 2 work-items), and under changing requirements that include different fault tolerance levels (Simplex for no redundancy, DMR, and TMR). The KC705 development board only has resources to host 6 accelerators, and therefore the embedded models, previously validated and verified experimentally with other kernels and FPGA boards [3], have been used in order to predict the behavior of the system when the number of accelerators is increased above this limit (dotted lines in the figures). Hence, the transition from computing-bounded to memory-bounded execution is clear: when maximum bus occupancy is reached, no further speedup can be achieved.…”

“…The resource manager has access in real time to runtime metrics such as power consumption, execution times or even bus occupancy, and it uses embedded models to achieve energy-efficient or even predictable execution [3]. As an example, Fig.…”

“…Moreover, self-aware resource management strategies to select the optimum operating point for any task provide complete independence between the task itself and the requirements at any given instant of time. Self-awareness and adaptivity are enhanced by accurate prediction models of task execution [3] that, together with the predictability given by the High Level Synthesis (HLS) tools proposed for the development of hardware accelerators, are an important step towards predictability in adaptive multithreaded hardware-accelerated architectures.…”

Run-Time Mitigation of Power Budget Variations and Hardware Faults by Structural Adaptation of FPGA-Based Multi-Modal SoPC

“…Methods like Dynamic Voltage and Frequency Scaling (DVFS) and DFS are used to control power consumption [25,26] and temperature [27] and also to sustain task performances in presence of temperature variations [28]. Dynamic scheduling techniques [27,[29][30][31][32] and dynamic mapping (or resource management) techniques [27,[33][34][35] are other methods used to achieve power and/or thermal aware workload management. Dynamic scheduling and mapping techniques are also employed for fault mitigation [15,36,37].…”

System-on-chip design of the cortical-diencephalic centre of the lower urinary tract

“…After creating the hardware design shown in Figure 6, we obtained an equivalent circuit implemented in FPGA, which uses the different resources summarised in Table 7. [46,47]. Additionally, the prototype uses 3497 of 8846 LUT-FF pairs, or 39% of the available resources.…”