Experimental Characterization of the Vertical Position of the Trapped Charge in Si Nitride-Based Nonvolatile Memory Cells

Arreghini, A.; Driussi, F.; Vianello, E.; Esseni, D.; Duuren, M.J. van; Golubović, D.S.; Akil, N.; Schaijk, R. van

doi:10.1109/ted.2008.919713

Cited by 49 publications

(33 citation statements)

References 22 publications

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“…In contrast, the reference [3] with a high-k (HfO 2 ) blocking layer and a thin SiN layer (5.7 nm) shows significantly different result, i.e. the charge centroid is located in the bulk region of the SiN layer.…”

Section: Ecs Transactions 35 (4) 417-446 (2011)mentioning

confidence: 94%

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Charge Trapping and Reliability Properties of MONOS Memory with High-k Blocking Layer

et al. 2011

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Carrier trapping and reliability characteristics during the cycling operation of metal-oxide-nitride-oxide-semiconductor (MONOS) devices with a high-k blocking layer (Al 2 O 3 ) have been studied by measuring the injected charge during programming and erasing (P/E). The evaluated charge centroid during P/E indicates that the traps near the SiN/Al 2 O 3 interface are filled at high electric field, while bulk traps in the SiN layer are also available at low electric field. The degradation of MONOS devices in cycling operation is found to be strongly correlated with injected charge during erasing. It is indispensable to suppress hole injection, as well as lowering the electric field to improve endurance of MONOS devices. The discussion of this paper also extends to the structure of the charge trapping layer to improve both cycling endurance and retention simultaneously. Finally, we report that a high-k blocking layer has significant impact on data readout and programming characteristics through its transient dielectric properties.

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Section: Ecs Transactions 35 (4) 417-446 (2011)mentioning

confidence: 94%

“…the charge centroid is located in the bulk region of the SiN layer. We believe that the difference originates from a thinner tunneling oxide of 2.2 nm used in [3] (i.e. direct tunneling region) where the electron energy is small in the SiN layer.…”

Section: Ecs Transactions 35 (4) 417-446 (2011)mentioning

confidence: 99%

Charge Trapping and Reliability Properties of MONOS Memory with High-k Blocking Layer

et al. 2011

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“…We always assume »c in the center of the charge trapping layer, as measured in [8], [9]. It is also worth noticing that in [8] »c computation resulted to be extremely affected by Q prog uncertainties ; therefore , the uncertainties on Xc that we possibly induce by our approximation of considering it in the center of the SiN, translate into small errors on the computed Q pr og .…”

Section: Ill D Evi C E D Escriptionmentioning

confidence: 99%

“…Both contributions need to be decoupled: this task is accomplished by theoretically computing Qpr og as the required charge to generate the measured~VT, according to the formula [8]: Finally, an alternative TANOS stack is also evaluated: this device features a thin (1 nm) Si0 2 Sealing Layer (SL) sandwiched between the SiN and AIO layers, and grown by ISSG oxidation. As discussed in [10], the role of the SL is to provide a larger ¢B , hence to improve programming and retention characteristics.…”

Section: Introductionmentioning

confidence: 99%

Experimental evaluation of trapping efficiency in silicon nitride based charge trapping memories

Suhane

Arreghini

bosch

et al. 2009

2009 Proceedings of the European Solid State Device Research Conference

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“…The information about the vertical location of tapped charges is crucial in understanding the trapping properties of Si 3 N 4 layer and for improving the performance and reliability of ReCTF devices. 7,8 However, the knowledge of the location of trapped charges in the nitride and the carrier transport during the P/E operations are not yet complete. It is necessary to understand the transient carrier capture dynamics by evaluating key parameters such as the charge centroid.…”

mentioning

confidence: 99%

Investigation of vertically trapped charge locations in Cr-doped-SrTiO3-based charge trapping memory devices

Seo

Song

et al. 2012

Journal of Applied Physics

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In this paper, vertically trapped charge location is investigated to understand the carrier-transport dynamics in chromium-doped strontium titanate (Cr-SrTiO3 (STO))-based charge trapping memory devices using a transient analysis method. The vertical location of trapped charges is found to move from the Cr-SrTiO3/Si3N4 interface to the bulk region of Si3N4 with an increasing of the electric field, and, particularly, available trap sites are limited at the Cr-SrTiO3/Si3N4 interface by hole injection from the Si substrate into the Si3N4 layer at a high electric field (EOX > 7 MV/cm). In addition, some of these charges passing across the SiO2 (OX) layer generate many Si-SiO2 interface traps (Dit: 1.58 × 1012 cm−2 eV−1) that may degrade the device. However, the trapping efficiency can be improved by using sufficiently thick ( > 10 nm) bottom layers and by preventing direct hole tunneling and thereby, reducing the interface trap density.

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Experimental Characterization of the Vertical Position of the Trapped Charge in Si Nitride-Based Nonvolatile Memory Cells

Cited by 49 publications

References 22 publications

Charge Trapping and Reliability Properties of MONOS Memory with High-k Blocking Layer

Charge Trapping and Reliability Properties of MONOS Memory with High-k Blocking Layer

Experimental evaluation of trapping efficiency in silicon nitride based charge trapping memories

Investigation of vertically trapped charge locations in Cr-doped-SrTiO3-based charge trapping memory devices

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