Experimental Demonstration of a 1-Bit Full Adder in Perpendicular Nanomagnetic Logic

Breitkreutz, Stephan; Kiermaier, Josef; Eichwald, Irina; Hildbrand, Christian; Csaba, G.; Schmitt‐Landsiedel, D.; Becherer, Markus

doi:10.1109/tmag.2013.2243704

Cited by 63 publications

(42 citation statements)

References 21 publications

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“…9 show that P nuc can have a remarkable impact on the reliability of pNML-based structures. To validate our model, we carried out different studies on the FA 9 and compared measurements with data obtained through simulations.…”

Section: Introductionmentioning

confidence: 92%

“…9 (with 200 nm wide [Co 0.8nm Pt 1.0nnm ] ×4 as case study. From a methodological point of view, the tested circuit is decomposed into basic blocks as depicted in Fig.…”

Section: A Case Study: Full Addermentioning

confidence: 99%

“…9, H clock = 560 Oe (Table I). The propagation time of the longest DW extracted performing the dummy simulation, the t prop,cr extracted is equal to 118 ns.…”

Section: A Case Study: Full Addermentioning

confidence: 99%

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A compact physical model for the simulation of pNML-based architectures

et al. 2017

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Controlled data storage for non-volatile memory cells embedded in nano magnetic logic AIP Advances 7, 055910 (2017) Among emerging technologies, perpendicular Nanomagnetic Logic (pNML) seems to be very promising because of its capability of combining logic and memory onto the same device, scalability, 3D-integration and low power consumption. Recently, Full Adder (FA) structures clocked by a global magnetic field have been experimentally demonstrated and detailed characterizations of the switching process governing the domain wall (DW) nucleation probability P nuc and time t nuc have been performed. However, the design of pNML architectures represent a crucial point in the study of this technology; this can have a remarkable impact on the reliability of pNML structures. Here, we present a compact model developed in VHDL which enables to simulate complex pNML architectures while keeping into account critical physical parameters. Therefore, such parameters have been extracted from the experiments, fitted by the corresponding physical equations and encapsulated into the proposed model.

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Section: Introductionmentioning

confidence: 92%

“…9 (with 200 nm wide [Co 0.8nm Pt 1.0nnm ] ×4 as case study. From a methodological point of view, the tested circuit is decomposed into basic blocks as depicted in Fig.…”

Section: A Case Study: Full Addermentioning

confidence: 99%

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A compact physical model for the simulation of pNML-based architectures

et al. 2017

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“…2c shows the layout of a NML inverter and majority gate. NML is the most mature and feasible of the considered technologies, with experimentally proven small in size circuits [24], and since its operation is based on individual nanomagnets, its non-volatility property is the largest of the technologies considered in this work. However, this means that the energy and delay required for operation are the highest among SWD, QCA, and NML.…”

Section: B Technology Implementationmentioning

confidence: 99%

“…BENCHMARKING RESULTS As mentioned in Section III, we use the MIG benchmarks from [16] to benchmark the proposed wave pipelining enablement. Table I introduces the primitive area, delay, and energy constants used for each technology, extracted from [22] for SWD, [12] for QCA and [11], [24] for NML. Additionally, Table I shows the relative cost for each component included in the wave pipelined enabled netlists.…”

Section: Fan-out Restrictionmentioning

confidence: 99%

Wave pipelining for majority-based beyond-CMOS technologies

Zografos

Meester

Testa

et al. 2017

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2017

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Abstract-The performance of some emerging nanotechnologies benefits from wave pipelining. The design of such circuits requires new models and algorithms. Thus we show how MajorityInverter Graphs (MIG) can be used for this purpose and we extend the related optimization algorithms. The resulting designs have increased throughput, something that has traditionally been a weak point for the majority of non-charge-based technologies. We benchmark the algorithm on MIG netlists with three different technologies, Spin Wave Devices (SWD), Quantum-dot Cellular Automata (QCA), and NanoMagnetic Logic (NML). We find that the wave pipelined version of the netlists have an improvement in throughput over power of 23×, 13×, and 5× for SWD, QCA, and NML, respectively. In terms of throughput over area ratio, the improvement is 5×, 8×, and 3×, respectively.

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Nanomagnet Logic

Csaba

Bernstein

Porod

et al. 2015

Wiley Encyclopedia of Electrical and Electronics Engineering

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Nanomagnet Logic (NML) is a circuit architecture that uses nanoscale magnets and their interactions to represent and process digital information. NML has been shown to be functionally equivalent to Boolean digital circuits, that is, able to perform all arithmetic/logic operations that today's omnipresent electronic computers can do. This article reviews the state of the art of NML devices.

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Experimental Demonstration of a 1-Bit Full Adder in Perpendicular Nanomagnetic Logic

Cited by 63 publications

References 21 publications

A compact physical model for the simulation of pNML-based architectures

A compact physical model for the simulation of pNML-based architectures

Wave pipelining for majority-based beyond-CMOS technologies

Nanomagnet Logic

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