Experimental demonstration of high source velocity and its enhancement by uniaxial stress in Ge PFETs

Kobabyashi, Masaharu; Mitard, J.; Irisawa, T.; Hoffmann, T.; Meuris, Marc; Saraswat, Krishna C.; Nishi, Yoshio; Heyns, Marc

doi:10.1109/vlsit.2010.5556233

Cited by 3 publications

(2 citation statements)

References 2 publications

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“…Strain is also promising for future technologies with novel channel materials including Ge and III-V semiconductors. The effectiveness of the uniaxial stress to velocity enhancement as a performance booster was experimentally demonstrated in short channel regime for Ge PFETs [60]. Strain and confinement also leads to reduction in effective mass in InGaSb/GaSb channels with the highest mobility reported at room temperatures [61], making the Sb-based channels promising candidates for future CMOS technologies.…”

Section: Strain Engineering For the Future Cmos Technologiesmentioning

confidence: 98%

Advanced strain engineering for state-of-the-art nanoscale CMOS technology

Yang

Cai

2011

Sci. China Inf. Sci.

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The introduction and advancement of strain engineering has been one of the most critical features for the state-of-the-art nanoscale CMOS transistors. This paper provides an overview of the major strain engineering techniques that have remarkably re-shaped the advanced CMOS transistor architecture, including embedded SiGe (eSiGe), embedded Si:C (eSi:C), stress memorization technique (SMT), dual stress liners (DSL), and stress proximity technique (SPT). The advent of high-K/metal-gate (HKMG) also brings in additional strain benefit with its metal gate stressor (MGS) and replacement gate (RMG) process. Strain engineering continues to evolve and will remain to be one of the key performance enablers for the future generation of CMOS technologies. CitationYang B, Cai M. Advanced strain engineering for state-of-the-art nanoscale CMOS technology. Sci China Inf Sci, 2011, 54: 946-958,

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Section: Strain Engineering For the Future Cmos Technologiesmentioning

confidence: 98%

Advanced strain engineering for state-of-the-art nanoscale CMOS technology

Yang

Cai

2011

Sci. China Inf. Sci.

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“…The most important advantages of the Schottky barrier device include low thermal budget, small serial resistance and parasitic capacitance, which make the Schottky barrier device has a good physical scalability confronted with short channel effect. [1][2][3][4][5][6][7] Meanwhile, in recent years, Ge-based MOSFETs have attracted much attention, [8][9][10][11][12][13][14][15] which is due to the outstanding field effect mobility and drivability. [16][17][18][19][20][21][22] Thus, Schottky barrier source=drain with germanium channel (SL-T) becomes one promising candidate for future structure.…”

Section: Introductionmentioning

confidence: 99%

New concept of planar germanium MOSFET with stacked germanide layers at source/drain

Xu¹,

Sun²,

Zhang³

et al. 2015

Jpn. J. Appl. Phys.

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Novel Schottky barrier Ge-based MOSFET structure is proposed and simulated. The Source/Drain region is consisted with two stacked layers of germanide materials. The barrier heights of the top and bottom layer are different. The working mechanism and performance of the device is studied. The results show that ON-state current, leakage current, and transfer characteristics have been enhanced with the proposed structure. Besides, the requirement of GOI structures for leakage immunization can be released.

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Higher κ metal-gate/high-κ/Ge n-MOSFETs with &#60;1 nm EOT using laser annealing

Chen

Shie

Chin

et al. 2010

2010 International Electron Devices Meeting

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High performance metal-gate/high-κ/Ge n-MOSFETs are reached with low 73 Ω/sq sheet resistance (R s ), 1.10 ideality factor, 0.95 nm EOT, small 106 mV/dec sub-threshold slope (SS), good 285 cm 2 /Vs high-field (1 MV/cm) mobility and low 37 mV ΔV t PBTI (85 o C, 1 hr). This is achieved by using 30-ns laser annealing that leads to 57% higher gate capacitance, better n + /p junction and 10X better I ON /I OFF .

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Experimental demonstration of high source velocity and its enhancement by uniaxial stress in Ge PFETs

Cited by 3 publications

References 2 publications

Advanced strain engineering for state-of-the-art nanoscale CMOS technology

Advanced strain engineering for state-of-the-art nanoscale CMOS technology

New concept of planar germanium MOSFET with stacked germanide layers at source/drain

Higher κ metal-gate/high-κ/Ge n-MOSFETs with &#60;1 nm EOT using laser annealing

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Experimental demonstration of high source velocity and its enhancement by uniaxial stress in Ge PFETs

Cited by 3 publications

References 2 publications

Advanced strain engineering for state-of-the-art nanoscale CMOS technology

Advanced strain engineering for state-of-the-art nanoscale CMOS technology

New concept of planar germanium MOSFET with stacked germanide layers at source/drain

Higher &#x03BA; metal-gate/high-&#x03BA;/Ge n-MOSFETs with &#38;#60;1 nm EOT using laser annealing

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Higher κ metal-gate/high-κ/Ge n-MOSFETs with <1 nm EOT using laser annealing