2022
DOI: 10.1109/ted.2021.3139285
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Experimental Extraction and Simulation of Charge Trapping During Endurance of FeFET With TiN/HfZrO/SiO2/Si (MFIS) Gate Structure

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Cited by 32 publications
(9 citation statements)
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“…Retention degradation has been a significant challenge for FeFETs over several decades. The loss of retention over time is attributed to two main reasons: the presence of a depolarization field due to a finite capacitance in series with the ferroelectric layer and the gate leakage followed by trapping and detrapping effect in the interface layers in the gate stack. Clearly, operation of a CAM cell can be affected because of this issue. If V th of the FeFET in our CAM cell increases with time, the match line (ML) and the sensed output voltage with respect to V SL will shift, as shown in Figure .…”
Section: Resultsmentioning
confidence: 99%
“…Retention degradation has been a significant challenge for FeFETs over several decades. The loss of retention over time is attributed to two main reasons: the presence of a depolarization field due to a finite capacitance in series with the ferroelectric layer and the gate leakage followed by trapping and detrapping effect in the interface layers in the gate stack. Clearly, operation of a CAM cell can be affected because of this issue. If V th of the FeFET in our CAM cell increases with time, the match line (ML) and the sensed output voltage with respect to V SL will shift, as shown in Figure .…”
Section: Resultsmentioning
confidence: 99%
“…Despite the obvious limitation that the MOSFET dimensions should be increased relative to the ferroelectric film, there is a clear advantage regarding memory characteristics and reliability when compared to the existing MFIS FeFET, which suffers from degradation of polarization switching and premature deterioration of the gate insulator owing to the ferroelectric film's high dielectric constant, as shown in Table S4 (ESI †). [27][28][29][30] Fig. 3(a) shows the capacitance ratio and memory window according to A FE /A MOS .…”
Section: Resultsmentioning
confidence: 99%
“…When voltage is applied to the device, the voltage is divided into the Hf 0.5 Zr 0.5 O 2 film and the SiO x IL based on the thickness and k ratio of each layer; for example, in a metal/10 nm Hf 0.5 Zr 0.5 O 2 ( k ∼30)/1 nm SiO x ( k ∼3.9)/Si MFIS capacitor, the applied voltage in the SiO x IL is 43% of the total applied voltage. A large voltage divided into the IL not only increases the operating voltage but also damages the IL itself and generates trap sites, severely limiting the reliability of the device. , …”
Section: Semiconductor–ferroelectric Interfacesmentioning
confidence: 99%