Experimental Investigation on the Quasi-Ballistic Transport: Part I—Determination of a New Backscattering Coefficient Extraction Methodology

Barral, V.; Poiroux, T.; Saint-Martin, Jérôme; Munteanu, Daniéla; Autran, Jean‐Luc; Deleonibus, S.

doi:10.1109/ted.2008.2011681

Cited by 43 publications

(27 citation statements)

References 27 publications

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“…The use of metal gates (or also FUSI) can mitigate the effect to some extent, but the channel-S/D interaction is intrinsic and unavoidable, barring the use of Schottky S/D contacts. Additional experimental evidence hinting at Coulomb effects as responsible for 'unexplained' performance degradation at short channel lengths has also been provided by Cros and co-workers [4], and by Barral et al [5,6], while 3D MC simulations [7,8] have confirmed the early 2D results. The effect can be simply understood.…”

Section: Coulomb Interactions and Historical Trends Of Si Nmos Performentioning

confidence: 67%

Scaling MOSFETs to 10 nm: Coulomb effects, source starvation, and virtual source model

et al. 2009

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In our attempts to scale FETs to the 10 nm length, alternatives to conventional Si CMOS are sought on the grounds that: (1) Si seems to have reached its technological and performance limits and (2) the use of alternative highmobility channel materials will provide the missing performance. With the help of numerical simulations here we establish the reasons why indeed Si seems to have hit an intrinsic performance barrier and whether or not high mobility semiconductors can indeed grant us our wishes. The role of long-and short-range electron-electron interactions are revisited together with a recent analysis of the historical performance trends. The density-of-states (DOS) bottleneck and source starvation issues are also reviewed to see what advantage alternative substrates may bring us. Finally, the well-known 'virtual source model' is analyzed to assess whether it can be used as a quantitative tool to guide us to the 10 nm gate length.

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Section: Coulomb Interactions and Historical Trends Of Si Nmos Performentioning

confidence: 67%

Scaling MOSFETs to 10 nm: Coulomb effects, source starvation, and virtual source model

et al. 2009

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“…I off levels in the pA/µm range have been obtained in these devices with Si thicknesses as low as 2.5 nm [35] (Figures 9 and 10). In this devices architecture, ballistic rates BR of 50% were obtained at room temperature and did not exceed 60% at 50 K (n and p MOS with T si =6 nm N INV =6 × 10 12 cm −2 ) [8,9].…”

Section: Quasi-ballistic Transport In Strained Fdsoi Devicesmentioning

confidence: 85%

“…However, in small devices, high electric fields affect the transport mechanisms. Therefore, transport must be considered quasi ballistic, involving: 1) repopulation of heavy effective mass sub-bands guided by degenerate statistics under high electric fields; and 2) backscattering of carriers by coulombic sites (interfaces and dopants) [6][7][8][9]. In the saturation regime, the drain current will be reduced by the ballisticity rate depending primarily on the backscattering of the injected carriers.…”

Section: Non Stationary Transportmentioning

confidence: 99%

Ultra-thin films and multigate devices architectures for future CMOS scaling

Deleonibus

2011

Sci. China Inf. Sci.

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The nanoelectronics industry is facing historical challenges to scale down CMOS devices to meet demands for low voltage, low power, high performance and increased functionality. Using new materials and devices architectures is necessary. HiK gate dielectrics and metal gates have been introduced and have shown their ability to reduce power consumption. Fully depleted ultra-thin SOI devices are a good alternative to bulk for low power applications. Multigate devices are the current goal in device architecture to increase MOSFET drivability, reduce power, and allow new opportunities for future applications. Thin film based solutions will be necessary in the future because of fundamental limitations on gate capacitance scaling and system integration requirements. Exploiting 3D device stacking via wafer bonding could be a good way to introduce new materials (HiK, strained Si, hybrid orientations, Ge, III-Vs, Carbon-based materials, graphene and CNTs, and functional molecules) and continue increasing integration density. Si based CMOS will be scaled beyond the ITRS as the System-on-Chip/Wafer Platform.The international technology roadmap of semiconductors (ITRS) [1] distinguishes three types of products: high performance (HP), low operating power (LOP) and low standby power (LSTP) devices. In the HP case, a landmark has been reached at the 32-nm node: the contribution from static power dissipation approaches the dynamic power contribution [2]. Multigate devices could improve this somewhat by increasing the saturation current to leakage current ratio.In this review, we will first analyze the primary limitations and showstoppers of CMOS scaling. Issues on gate stack, channel and source and drain engineering as well as new device architectures (FDSOI or multigate devices) are discussed.Low power consumption and heterogeneous function integration will be leveraged by future nomadic systems. The increased number of devices and different types of signals will, in turn, require the leveraging of 3D IN package or ON chip co-integration. Limitations, showstoppers and opportunities of Si CMOS scalingCMOS device engineering consists of minimizing leakage current and the maximization of output current. In sub-100-nm CMOS devices, non-stationary transport is more important than diffusive transport. To this end, several questions arise related to the origins of the leakage currents, non-stationary transport limitations and supply voltage scaling.

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“…A summary of the extracted macroscopic parameters of the IFQW-CMOS is shown in Table II. There, the "effective source velocity" is a measure of the average velocity at the source end of the channel [36], a product of classical injection velocity and ballistic ratio [37].…”

Section: Access Resistancesmentioning

confidence: 99%

Device and Circuit Performance of the Future Hybrid III–V and Ge-Based CMOS Technology

Benbakhti

Chan

Soltani

et al. 2016

IEEE Trans. Electron Devices

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Abstract-The device and circuit performance of a 20 nm gate length InGaAs and Ge hybrid CMOS based on an implant free quantum well (QW) device architecture is studied using a multiscale approach combining ensemble Monte Carlo simulation, drift-diffusion simulation, compact modelling, and TCAD mixedmode circuit simulation. We have found that the QW and doped substrate, used in the hybrid CMOS, help to reduce short channel effects by enhancing carrier confinement. The QW also reduces the destructive impact of a low density of states (DoS) in III-V materials. In addition, the calculated access resistance is found to be a much lower than in Si counterparts thanks to a heavily doped overgrowth source/drain contact. We predict an overall low gate capacitance and a large drive current when compared to Si-CMOS that leads to a significant reduction in a circuit propagation time delay (∼5.5 ps).

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Experimental Investigation on the Quasi-Ballistic Transport: Part I—Determination of a New Backscattering Coefficient Extraction Methodology

Cited by 43 publications

References 27 publications

Scaling MOSFETs to 10 nm: Coulomb effects, source starvation, and virtual source model

Scaling MOSFETs to 10 nm: Coulomb effects, source starvation, and virtual source model

Ultra-thin films and multigate devices architectures for future CMOS scaling

Device and Circuit Performance of the Future Hybrid III–V and Ge-Based CMOS Technology

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