2013 IEEE International Electron Devices Meeting 2013
DOI: 10.1109/iedm.2013.6724709
|View full text |Cite
|
Sign up to set email alerts
|

Experimental observation and physics of &#x201C;negative&#x201D; capacitance and steeper than 40mV/decade subthreshold swing in Al<inf>0.83</inf>In<inf>0.17</inf>N/AlN/GaN MOS-HEMT on SiC substrate

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
3
1
1

Citation Types

0
24
1

Year Published

2015
2015
2022
2022

Publication Types

Select...
8

Relationship

0
8

Authors

Journals

citations
Cited by 29 publications
(25 citation statements)
references
References 8 publications
0
24
1
Order By: Relevance
“…Figure 6 summarizes the GaN-based devices on Si, SiC, and sapphire substrates for ON/OFF ratio and subthreshold swing [7,10,19,20,21,22,23]. This study demonstrates the InAlN barrier GaN MOS-HEMT for SS <60 mV/dec (reverse sweep SS = 28 mV/dec) with the first time directly-on-Si and outstanding performance with high ON/OFF ratio (~10 7 ).…”
Section: Resultsmentioning
confidence: 91%
See 1 more Smart Citation
“…Figure 6 summarizes the GaN-based devices on Si, SiC, and sapphire substrates for ON/OFF ratio and subthreshold swing [7,10,19,20,21,22,23]. This study demonstrates the InAlN barrier GaN MOS-HEMT for SS <60 mV/dec (reverse sweep SS = 28 mV/dec) with the first time directly-on-Si and outstanding performance with high ON/OFF ratio (~10 7 ).…”
Section: Resultsmentioning
confidence: 91%
“…The InAlN/GaN on Si with ~10 7 and 10 8 ON/OFF ratio with Ohmic and hybrid source/drain, respectively, is reported [8,9]. Intel exhibits a near ideal 60 mV/dec of subthreshold swing for MIS-HEMT enhancement mode, and a depletion mode device with steep SS < 60 mV/dec because of “negative” capacitance effect is shown using an AlInN metal-oxide-semiconductor (MOS) HEMT on SiC [10]. The negative capacitance concept is already demonstrated for steep switching on the Complementary Metal-Oxide-Semiconductor (CMOS) platform, including experimental and simulation development [11].…”
Section: Introductionmentioning
confidence: 99%
“…In this regime of negative capacitance, we show that we obtain a higher charge than in a corresponding capacitor with a passive dielectric. Non-trivial capacitancevoltage behavior in such capacitors have also been reported experimentally [10], [11]. Next, we port the parallel-plate electromechanical capacitor to the gate capacitor of a FET.…”
Section: Introductionmentioning
confidence: 75%
“…Quantum-well MOSFETs [8] 81 InGaZnO-Based Thin-Film Transistor [9] 85 Al 0.83 In 0.17 N/AlN/GaN MOS-HEMT on SiC Substrate [10] 40 The nothing-on-insulator (NOI) transistor [11,12] 50 Metal-Ferroelectric-Insulator [13] 150 Double-Gate Strained-Ge Heterostructure Tunneling FET [14] 52 Fe-FET with P(VDF-TrFE)/SiO2 Gate Stack [13] 13 Metal-Ferroelectric-Metal-Oxide-Semiconductor FET [15] 46-58 Vertical Si-Nanowire n-Type Tunneling FETs [16] 30 would bring transformative change in the performance and energy efficiency of both ultra-low-power and high performance micro-/nano-electronic applications. We formally named this new device Silicon-on-Ferroelectric Insulator Field Effect (SOFFET) [20,21].…”
Section: Structurementioning
confidence: 99%