Experimental results for IDDQ and VLV testing

“…Traditionally, test methods have been evaluated empirically. Specifically, silicon experiments are conducted to reveal real defect characteristics and for assessing the capability of various test and DFT methods to detect chip failures [4,5,14,16,17,[20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36]. Unique fallouts (i.e., chip-failure detections) are considered to be good indicators of relative effectiveness.…”

Section: Introductionmentioning

confidence: 99%

Test effectiveness evaluation through analysis of readily-available tester data

Lin

Blanton

2009

2009 International Test Conference

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Test metrics and fault models continue to evolve to keep up with defect characteristics associated with ever-changing fabrication processes. Understanding the relative effectiveness of current and proposed metrics and models is therefore important for selecting the best mix of methods for achieving a desired level of quality at reasonable cost. Test-metric and fault model evaluation traditionally relies on large, time-consuming silicon-based test experiments. Specifically, tests generated for some specific metric/model are applied to real chips, and unique chip-fail detections are used as relative measures of effectiveness. To reduce the cost of evaluating new test metrics, fault models, DFT techniques, etc., this work proposes a new approach that exploits the readily-available test-measurement data in chip-failure log files. The new approach does not require the generation and application of new patterns but uses analysis results from existing tests. We demonstrate the method by comparing several metrics and models that include: (i) stuck-at, (ii) N-detect, (iii) PAN-detect (physically-aware N-detect), (iv) bridge fault models, and (v) the input pattern fault model (also more recently referred to as the gate-exhaustive metric).

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“…Different with the experimental studies in [9][10], our test chips were injected with delay faults and the output path delays, delay fault size and the normal parameter variations were recorded at multiple VDD. We showed that the delay faults were reliably detected by using DDSI in low voltage test mode.…”

Section: Resultsmentioning

confidence: 99%