Experimental Verification of Scan-Architecture-Based Evaluation Technique of SET and SEU Soft-Error Rates at Each Flip-Flop in Logic VLSI Systems

Yanagawa, Yoshimitsu; Kobayashi, Daisuke; Hirose, Kazuyuki; Makino, Takahiro; Saito, Hirobumi; Ikeda, Hirokazu; Onoda, Shinobu; Hirao, Toshio; Ohshima, Takeshi

doi:10.1109/tns.2009.2020166

Cited by 11 publications

(6 citation statements)

References 16 publications

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“…Compared with the bulk inverter, the FD SOI one provides lower radiation sensitivity (or lower cross sections) as well as shorter SET pulses. Figure 8 tion tendency for the pulse width (27) and validated the theoretical calculation technique for estimating bit-distortion probability (28,29).…”

Section: Pulse-width Measurementsmentioning

confidence: 62%

Radiation-Induced Pulse Noise in SOI CMOS Logic

Kobayashi¹,

Hirose²,

Ikeda³

et al. 2011

ECS Trans.

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A comprehensive study on radiation-induced pulse noises in SOI CMOS logic is reviewed. The noise pulses are called single event transients or SETs and becoming a serious source of soft errors in logic systems. As a result of miniaturization of transistors, concern about the soft error problems caused by the SETs are growing not only in special applications for harsh radiation environments like space but also in usual ones used on the ground. It is important to reveal what the SET is in its nature. Measurement techniques and analytical model have been developed for the purpose.They are introduced together with experimental data obtained with test circuits fabricated by a commercial 0.2-micrometer fully-depleted SOI technology. Issues to be solved for use of SOI technologies in realizing radiation hardened devices are also described with a practical example, or a development process of radiation hardened SOI SRAMs.

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Section: Pulse-width Measurementsmentioning

confidence: 62%

Radiation-Induced Pulse Noise in SOI CMOS Logic

Kobayashi¹,

Hirose²,

Ikeda³

et al. 2011

ECS Trans.

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“…They can dominate the heavy-ion-induced soft-error response of modern digital logic very-large-scale-integrations (VLSIs) [1]. Since the pulse-width (duration) of DSETs is a key parameter in determining the soft error rates in logic VLSIs, the DSET pulse-widths have been extensively measured by using logic cell chains, and specially built pulse capture circuits such as variable temporal latches, self-triggering latches/flip-flops, and high drive-capability output-buffers [2][3][4][5][6][7][8][9][10]. These circuits allow us to observe the widths of the DSET pulse originating in actual logic cells under ion irradiation test conditions.…”

Section: Introductionmentioning

confidence: 99%

“…These circuits allow us to observe the widths of the DSET pulse originating in actual logic cells under ion irradiation test conditions. The heavy-ion-induced DSET pulse-widths and the DSET cross-sections in 0.2 µm fully-depleted silicon-on-insulator (FD-SOI) process inverter cells and NOR cells by using the on-chip self-triggering flip-flop latch chain named Snapshot has also been measured [3,7,9,10].…”

Section: Introductionmentioning

confidence: 99%

A Methodology for Reconstructing DSET Pulses from Heavy-Ion Broad-Beam Measurements

Makino

Onoda

Ohshima

et al. 2020

QuBS

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A table-based method for the estimation of heavy-ion-induced Digital Single Event Transient (DSET) voltage pulse-width in a single logic cell has been developed. The estimation method is based on the actual heavy-ion-induced transient current data in a single metal-oxide-semiconductor field effect transistor (MOSFET) used in the logic cell. The DSET pulse waveform in an inverter is obtained from which the pulse-width was estimated to be 420 ps. This DSET pulse-width value (420 ps) falls within the reasonable range of the DSET pulse-width distribution measured by the self-triggering flip-flop latch chain under heavy-ion irradiation test conditions.

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“…Hence beam-based tests are widely performed using various types of beams. The beam may be a radiation particle beam, 7,8) which is emitted by a particle accelerator such as a cyclotron, but the use of such sources can be concomitant with problems such as limited access and beam control. In this regard, pulsed laser systems, because they can be installed on a laboratory bench, have been used as a complementary tool.…”

Section: Introductionmentioning

confidence: 99%

Spatial resolution of soft-error sensitive-depth analysis by scanning two-photon absorption laser microscopy

Itsuji

Kobayashi

Hirose

2020

Jpn. J. Appl. Phys.

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Soft errors are widely recognized as a reliability issue, and are a circuit malfunction caused by particle radiation. Identifying soft-error sensitive volumes of a semiconductor circuit is useful for evaluating soft-error sensitivity and developing countermeasures against soft errors. This paper quantifies the spatial resolution of soft-error sensitive-volume analysis by scanning two-photon absorption laser microscopy. We identify the critical parameter determining the spatial resolution in the depth direction and demonstrate that optimal parameter selection can extract soft-error sensitive depths of current LSIs.

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Experimental Verification of Scan-Architecture-Based Evaluation Technique of SET and SEU Soft-Error Rates at Each Flip-Flop in Logic VLSI Systems

Cited by 11 publications

References 16 publications

Radiation-Induced Pulse Noise in SOI CMOS Logic

Radiation-Induced Pulse Noise in SOI CMOS Logic

A Methodology for Reconstructing DSET Pulses from Heavy-Ion Broad-Beam Measurements

Spatial resolution of soft-error sensitive-depth analysis by scanning two-photon absorption laser microscopy

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